Respected Experts,
I would like to know that is it possible to get the advantage of Hardware Asssited Virtualization to develop a Type 2 Hypervisor which runs on …
Respected Experts,
I would like to know that is it possible to get the advantage of Hardware Asssited Virtualization to develop a Type 2 Hypervisor which runs on …
Hello,
In the new v8.2, atomic instructions are presented which can be an alternative to the previous ld/st exclusive and other similar instructions.
My question is what is the advantage of using atomic instructions instead of for example a pair of ld…
Hi ARM expert,
I need do something when dealing with the access flag fault. But in ARMv8.1-A, there is an option of hardware management of the Access flag. Can anybody tell me how to set the option?
Thank a lot.
How does atomicity work with the memory accesses?
Hi Experts,
I have a question about "STP" instruction in Cortex-A53.
STP W6, W6, [SP, #20] --> after it executes, the memory of [sp, #16] and [sp, #28] are corrupted.
I don't know why cause it.
Can you help to explain the reason…
Hi !
I am currently using the Access Flag with software management, and I recently read about the v8.1 evolution with hardware management. From the reference manual:
When the hardware management of the Access flag is enabled, in situations where, without…