• Aarch32 app performance on ARMv8a device

    Sreenath P V
    Sreenath P V

    Hi ,

    I am running aarch32 app in ARMv8a( cortex-a57 ) device.  The performance reports ( using gettimeofday() utility ), showing  large spikes on random calls. But the same app on ARMv7a( cortex-a15 ) device is quite stable.

    Will the aarch32 library…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum

  • How to get the secure(or non-secure) state on Cortex-A53?

    Brian Kim
    Brian Kim

    Could anyone give me the code to get the current secure state?

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum

  • CORTEX-A processor interrupt handling

    Girish Raghavendran
    Girish Raghavendran

    Since I am currently reading lot of ARM documents to understand the architecture as a whole, I request you to mention as to what happens in case of CORTEX-A processor in the nested interrupt handler implementation since we have a SPSR in CORTEX-A processors…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum

  • Performance effect because of removing some instructions from ARMv8?

    Natesh Raina
    Natesh Raina

    I was going through the ARMv8 Architecture Reference Manual and I came to know that it does not support many instructions that were previously supported by ARMv7 architecture. For example ARMv8 does not support conditional codes and have a seperate instruction…

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum

  • reason for ARMv8 EDSCR err bit set

    Strong
    Strong

    Hi,

    I'm working on a project which is for debugging cortex-a53 through Jtag interface.

    The Jtag clock TCK is set to 300kHz which is pretty low, and I can properly read back debug registers such as EDSCR and EDPRSR. EDPRSR is 1 before I issue the 'halt…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum

  • is it necessary for ARM-v8 soc to flush L2 cache to DRAM ?

    RadarSong
    RadarSong

    hi :

    I know , we can flush L1 I/D cache items to PoU with kernel interface(flush_cache_*).

    however, I can not find any clue about flushing L2 cache to DRAM(if without L3). 

    and I saw some points that L2 flushing was not needed.

    for ARMv8,  how can…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum

  • ARM Zynq Cortex-A53: implementing complex matrix inversion

    Laurent38
    Laurent38

    Hello,

    I am developing embedded software on Zynq MPSOC Cortex-A53 (Armv7/Armv8) for image processing, and I need some help for developing a specific algorithm.

    The algorithm involves many calculations of FFT and matrix using. As highest priority, we…

    • over 1 year ago
    • System
    • Embedded forum

  • dsb and dmb

    digital_kevin
    digital_kevin

    Hi all:

    I have some questions about DMB and DSB in armv8.

    (1)

    In armv8 Reference Manual doc, it says "The DMB instruction does not ensure the completion of any of the memory accesses for which it ensures relative order".

    But in ARM Cortex-A…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum

  • does ARM v8 bus architecture & related IPs be compatible with v7 core?

    chengliang
    chengliang

    I would like to get some confirmation that if we replace A53/A72 with A7/A9 while the SoC architecture is still based on ARM v8 bus & IPs (e.g. CCI400, NIC400, TZC400, GIC500, BP141), does such design feasible and workable?

    • over 3 years ago
    • System
    • SoC Design forum

  • Transition to secure monitor flow on ARMv8

    Umair Khan
    Umair Khan

    Hi everyone,

    Wherever I go on internet, the thing I read is that when SMC instruction is executed an exception is generated, it takes you to the highest exception level (EL3) where secure monitor is running.

    In ARM v8 vector table, given on ARMv8-A architecture…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum

  • Cortex A53 Debug using DSTREAM

    premchandh
    premchandh

    I am working with an S32V234 (NXP) branded ARMv8 Cortex-A53. I am trying to bring the board up in a secure way.I'm using DS-5 Development Studio Ultimate edition.I created a sample C Project. For flashing my code on that ARM Core.Firstly I Configured…

    • over 1 year ago
    • Software Tools
    • Arm Development Studio forum

  • Branch Predictor detailed info

    techguyz
    techguyz

    Hi all,

    Is there any document related to the branch predictor algorithm utilized in the ARMV7 and ARMV8 and how the software (ABI) can be aptly developed ac-complying the same ?

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum

  • OS store and restore registers

    techguyz
    techguyz

    Hi all,

    There is a dedicated register for store and restoring the OS thread context informations in ARMV8. What is the advantage of it and what is the use case of the same ??

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum

  • Does ARMV8 has Cortex M series

    techguyz
    techguyz

    Hi all,

    The new core ARM V8 supports A & R series alone M series are also be released in near future ?

    If not why ?

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum

  • 联发科10核进发 下季量产出货

    wangyong
    wangyong

         近期大陆手机产业内盛传手机晶片厂联发科面临高通、英特尔的激烈竞争已经疯了！将再掀起“核战”推出10核心手机晶片Hileo X20。据瞭解，目前被看衰第2季成长不到两成的联发科，确实将推出10核心晶片，最快在今年第3季出货为下半年旺季新添战斗力，让终端客户可以赶在年底 前上市销售新一代高阶机种。

         不过，联发科这次不是为了打核战，而是着眼于推出独步全球的创新3架构公板设计，引领手机和汽车一样进入Turbo高效节能时代，企图抢攻高通的高阶手机晶片市场…

    • over 5 years ago
    • 中文社区
    • 中文社区博客

  • [新闻稿]ARM为高端移动体验树立全新标杆

    Song Bin 宋斌
    Song Bin 宋斌

    新闻要点:

    ·         基于ARMv8-A架构的最新处理器ARM® Cortex®-A72，性能较五年前的处理器提升50倍

    ·         最新ARM CoreLink™ CCI-500高速缓存一致性互连（Cache Coherent Interconnect）允许更大的系统带宽…

    • over 5 years ago
    • 中文社区
    • 中文社区博客

  • Critical interrupts

    Michael Williams
    Michael Williams

    In software there are often cases where you need to have critical interrupts serviced. For example, for:

    • Code profiling
    • Kernel debugging
    • Watchdog handling
    • Error handling.

    With the ARMv7-M architecture this can be achieved using nested interrupt handlers, but…

    • over 5 years ago
    • Processors
    • Processors blog

  • Cavium发表48核ARM架构处理器，主攻数据中心与云端应用

    wangyong
    wangyong

    近几年来，想透过基于64位元ARMv8架构的系统单晶片（SoC），一举进军伺服器领域的厂商越来越多，目前，市面上可以看到AMD、Applied Micro、Cavium、Calxeda、Marvell、Nvidia、Samsung、Qualcomm，这几家公司动作频频，积极开发运算晶片，以满足新兴的微型伺服器应用。
    今年台北电脑展期间，ARM伺服器的发展动态自然也是全球瞩目的焦点之一，其中Cavium动作最快，在2014台北国际电脑展第一天，抢先发布了ThunderX系列伺服器级处理器，这系列采用64位元…

    • over 6 years ago
    • 中文社区
    • 中文社区博客

  • 深解ARM最强64位处理器 ARMv8架构厉害在何处?

    张超
    张超

    [导读] ARMv8是一个真正意义上的64位，同时这个64位的架构当中加入了或者说提供了32位的支持。Cortex-A57是ARM最先进、性能最高的应用处理器，而Cortex-A53不仅是功耗效率最高的ARM应用处理器，也是全球最小的64位处理器。

    ARMv8是一个真正意义上的64位，同时这个64位的架构当中加入了或者说提供了32位的支持。

    Cortex-A57是ARM最先进、性能最高的应用处理器，而Cortex-A53不仅是功耗效率最高的ARM应用处理器，也是全球最小的64位处理器。这两款处理器可各自独立运作或整合为ARM…

    • over 6 years ago
    • 中文社区
    • 中文社区博客

  • Let’s talk ACPI for Servers

    Andrew N. Sloss
    Andrew N. Sloss

    Before we do a dive into the ACPI standard, let’s go back to what the main goal is for firmware. Utopia is to have a universal firmware solution which can boot and support any Operating System (open, propriety and future) and any version of that Operating…

    • over 6 years ago
    • Processors
    • Processors blog

  • ARM Architecture Reference Manual for ARMv8-A (64-bit) publicly released

    Andrew N. Sloss
    Andrew N. Sloss

    This blog was originally posted on 11 September 2013 on blogs.arm.com

    Following on from the UEFI 64-bit announcement, I like to announce the release of the ARM® Architecture Reference Manual (commonly known as the ARM ARM) for ARMv8-A. This is a significant…

    • over 6 years ago
    • Processors
    • Processors blog

  • 引发下一次移动计算革命-ARMv8 SoC处理器

    Song Bin 宋斌
    Song Bin 宋斌

    原作者:brianjeff

    原文地址：Enabling the Next Mobile Computing Revolution - ARMv8-A SoC Processors

    我最近有机会去回忆过去五年中的移动计算革命。 我之所以专门用“移动计算”这个词，主要是因为我们在移动电话上能处理的任务已经和过去几年中我们只能在笔记本电脑或者台式机上处理的不相上下了。因为笔记本和台式机有来自墙角电源的不间断供电，所以他们需要风扇来冷却， 这也是他们的架构设计的基础。而今天的移动设备一次充电就能和他们一样工作一天…

    • ARM和高通-用高度集成ARMv8-A的SoC引发下一次移动计算革命.PDF
    • over 5 years ago
    • 中文社区
    • 中文社区博客