hi :

I know , we can flush L1 I/D cache items to PoU with kernel interface(flush_cache_*).

however, I can not find any clue about flushing L2 cache to DRAM(if without L3). 

and I saw some points that L2 flushing was not needed.

for ARMv8,  how can…

arm工程师，你好！

     我想咨询一下，关于如何在编写armv8汇编代码时，借助arm中cache来提升汇编函数的效率？一般情况下能提升多少？是否有此相关的详细文档？谢谢！