• Exceptions levels in the ARMv8 architecture

    Eivind
    Eivind

    Hello

    There are four exceptions levels in the ARMv8 architecture.

    EL0
    EL1
    EL2

    EL3

    Can anyone explain more of the EL3 execption level? What does it mean by 'allows swtiching between secure and nonsecure processor states? Secure monitor?

    Thanks

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum

  • is it necessary for ARM-v8 soc to flush L2 cache to DRAM ?

    RadarSong
    RadarSong

    hi :

    I know , we can flush L1 I/D cache items to PoU with kernel interface(flush_cache_*).

    however, I can not find any clue about flushing L2 cache to DRAM(if without L3). 

    and I saw some points that L2 flushing was not needed.

    for ARMv8,  how can…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum

  • Introducing 2017’s extensions to the Arm Architecture

    Matthew Gretton-Dann
    Matthew Gretton-Dann

    Introduction

    The Arm Architecture is continually evolving, and this blog gives a high-level overview of some of the changes made in Armv8.4-A*. We develop these changes by listening to the Arm Ecosystem and working with them to provide new functionality…

    • over 2 years ago
    • Processors
    • Processors blog

  • Issue with stxr in ARMv8

    armdev
    armdev

    Hi,

    I am writing a simple spinlock taking Juno arm trusted firmware spinlock code.

    But for me stxr instruction is always failing giving w1 value as "1" always.

    When I read ARMv8 spec it says (under section B2.10.5) "Unpredictable behavior when…

    • Answered
    • over 5 years ago
    • Open Source Software and Platforms
    • Arm Development Platforms forum