Hello,
My App (cortex m4) needs to set up a breakpoint directly from code, in order to jump to an interrupt when an instruction from a certain address is fetched.
This without using a debugger.
I searched in the forum and tried the method.
1. DebugMon…
I am working with an ARMv7-M with a cache and trying to workout how the Speculative data fetching works or at least understand it.
The only documentation I can find for it is a small section in ARM®v7-M Architecture Reference Manual.
Any resources to…
I am working with an ARMv7-M with a cache and trying to workout how the Speculative data fetching works or at least understand it.
The only documentation I can find for it is a small section in ARM®v7-M Architecture Reference Manual.
Any resources…
Hello
I've a question regarding the NVIC on Cortex M4 devices. Up until today I was under the impression that changing the priorities of a running interrupt isn't an issue in the ARMv7-M architecture, but the following pseudo-code snippet keeps triggering…
Hello,
in the ARMv7M Architecture Reference Manual version E.d in the documentation for "MVN (immediate)" on page A7-303 it says:
"<const> Specifies the immediate value to be added to the value obtained from <Rn>"
What is…
Hi,
I find C code not executing in the desired way. Then I step in assembly code of Tiva-C M4F core. Below is the disassembly code:
$C$L5: nop
0000033a: 280A CMP R0, #10…
Hi all,
I'm trying to understand the LDREX/STREX commands in an ARM Cortex M3 MCU to implement atomic access to various variables (the goal is to implement semaphores/mutexes or increment/decrement shared variables).
There are several ressources available…
Hi All,
I want to measure MIPS(Million Instruction per second, i.e. instruction count per second) on ARMv7 Platforms. What is the procedure for calculating MIPS for ARMv7 platforms?
Thanks and Regards
Sridhar Artham
Dear sirs,
The ARM v7ar manual says that DCC data registers DBGDTRTX and DBGDTRRX have RW attributes from external view.
It confuses me why DBGDTRTX can be written from external debugger. what is the purpose for this function?
The same confusion to DBGDTRRX…
Dear sirs,
Regarding v7m debug architecture, I have some questions after reading the v7m architecture document.
Q1: There is no mechanism to send instruction to the core for execution in debug state, is that true?
I guess the architecture uses debug return…
Hello All,
Good Morning!
I am working on Cortex m4.
I have read following about hard fault ,
"Bus Fault: detects memory access errors on instruction fetch, data read/write, interrupt vector fetch, and register stacking (save/restore) on interrupt (entry/exit…
I am seeing stack corruption running a Cortex M4 that seems to be related to interrupting multicycle instructions.
The interrupt occurs during a STMDB sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
The ICI bits at the time of the interrupt equal 7. This means that…
Hi,
I have been reading about the exception mechanism of Cortex-M (M4 to be precise). The exception request is accepted by the processor if the current priority level of the processor is less than the incoming exception (this is one of the conditions to…
I want to communicate NXP LPC2378 (ARM7 core) to some other devices via SPI (Serial Peripheral Interface) protocol.
So how to write a C code to communicate a particular device as a Slave with Master (ARM7 controller)?
I believe that many of us are interested in the ARM Cortex-M7.
Recently, jyiu posted a status update, where I asked a couple of questions about the architecture.
A few questions on the subject was also asked in the Interview and Question Time with Joseph…
I need some indications to begin writing a program.
Write a compare routine to compare 64-bits values , using only two instructions.
Thanks for your indications !
Hi, I am new to ARMv8 architecture and while reading the v8 exception vectors I am not able to understand significance of adding SP_EL0 level vectors while SP_ELx vector set exists. What I am trying to find a use case where this is useful. I understand…
Dear all,
I am interested in a scenario where I want to host two guest OSes above a bare-metal hypervisor on an ARM mobile platform. The total available memory platform is 4GB where I want to expose exclusively 2 GB of continuous RAM to each guest OS.…
what are the minimum hardware requirements to setup wifi on arm-7 processors.
Greetings,
Sir,i am working on SWD, after Research on Break Point & Watch Point i found One Thing That There are Some Comparators will Do These Things but I am not Very Sure That How These are Work …
There's many references to Debugging a Hard Fault on Cortex-M3 & M4; eg
niallcooling's Developing a Generic Hard Fault handler for Armv7-M
also:
Hello,
I am looking to do a moving average function using DSP instructions of ARM Cortex M7. Unfortunately I couldn't find a direct example. My goal is to have variables for
- the sum
- the new value
- the oldest value
Then the algorithm is sum =…
How to load the two’s complement representation of -1 into Register 3 using one instruction?
i am working on ARM7 and NXP processor.
Hello to all,
I am working on ARM Cortex-M4. Since it has 32-bit address bus, therefore I assumed that each 32-bit instruction will be allocated a physical address location in the Flash. But while reading the disassembly of the code, I got to know that…
The ARMv7-M reference manual notes there eight ITM trace enable registers called ITM_TER0 to ITM_TER7. However, core_cm7.h only has one ITM_TER register. Can you clarify? Is it an error in core_cm7.h?
