Secure SPI : STM32MP157-DK1 board

Simon

Hey everyone,

I am working on STM32MP157-DK1 with trustzone cortex-A.
I want to use the SPI in secure side, but it's possible only with SPI 6 that is not mapped to the outside.

It's possible to activate SPI (1 ... 5) peripherals in secure side ? if…

How to schedule Secure/Normal kernels in TrustZone implementation?

Kaiyuan

I read TZ whitepaper. TZ's software architecture includes normal OS, secure OS, and a monitor that manages switching between two OS. The notion is clear. But how to implement them confuses me.

Running and managing two kernels on a SoC needs mechanism…

Answered

Memory barrier (DSB, DMB). Does they guarantee writing data on cache to memory?

Yeo Reum Yun

Hi Experts,

I'm reading white paper for ARMv7 and ARMv8.

but when i reading cache part and memory re-ordering, i have silly questions.....

Suppose there are below instructions..

Core A:

STR R0, [Msg]

STR R1, [Something…

Answered

Which component will program TZASC?

Sahil

I have read in one ARM document

The TrustZone Address Space Controller (TZASC) is an AXI component which partitions its slave address range into a number of memory regions. The TZASC can be programmed by Secure software to configure these regions as Secure…

Answered

Trustzone FIQ latency measurement When security extension is enabled

Ashwin

Hello Guys,

Please refer below attached image. as shown in this image i want to measure the different latencies in my Trustzone based application.

Here is the list of measurements which i want to perform.

1) FIQ latency when RTOS runs and FIQ occurs …

Answered

Arm Technical Training – Any time, any place

Matt_Rushton

Partner Training at Arm has been a great success over the last 15 years. It has expanded the knowledge and capabilities of our Partners’ Engineering teams by delivering classroom sessions to over 4000 attendees in 2016 alone and has helped our Partners…

over 2 years ago
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