Hi everybody!!

I have a question on how get cache size on ARM v7-A, more specifically on A9 (or A7 or A15).

In accordance with the TRM at page 1529 I get the value from CSSIDR register and I compute the cache size. More precisely, I do cache size = num…

Hello everbody,

as i have written before in "Compability between architecture ARMv5TE and ARMv7-A", we want to change our Platform-Processor from ARM946E-S to an ARM Cortex-A9. The next Point in our risk disclosure ist the stack alignment.

Our…

Can anyone help?

Hi Experts,

A8 is meant for single core and A9 is for multi-core based.

Consider in case of SoC is build with single core of A9 and A8 how we could compare both in terms of some metrics/parameters like power/speed ?

When using gcc to compile c code for ARM platform, we set object platform by using:

     -mcpu = xxxxxx

To what extent will that affect results of compiling ?

For example:

     -mcpu = cortex-a8

and

     -mcpu = cortex…

Hello everyone, my 1st question to the ARM community; please excuse my ignorance.  Fairly recently, I shared OCM (on-chip-memory) on Xilinx Zynq processor (which is dual ARM Cortex A9).  To pass message between the 2 cores, I followed the Xilinx example…

Hi

my situation: Running an OS in normal-world which due to an (user) error enters safe state with interrupts disabled. The Hypervisor enters by an FIQ (watchdog) and should reset the normal-world.

No the problem: If the normal-world error happens in an…

When two clusters(Big/Little) exist in SoC, the timer can be used to support Synchronization between two clusters.

But How to understand "Synchronization", anybody can tell me some typical application context? I am really confused......

And, if…

Hi, all

What is the content of Context ID Register of ARM Cortex A9. Is it OS that is responsible for assigning the value

of Process ID and ASID? As far as I know, it is so in Linux. Is that the same in the other OSes?

Is it essential to deal with ASID if…

Hello,

I want to benchmark my program running on Linux on an Altera Cyclone V SoC board, but it turns out that the values returned from the ARM Cortex-A9 PMU cycle counter suggest that some sort of CPU frequency scaling is active, which is confusing me…

Hi Experts,

Is there any document on feature wise comparison chart on the Cortex A series of processors ?

Like,

Cache for Cortex A8/9/52...

MMU for cortex A8/9/52..

I'm measuring worst case execution time of an application. I would like to flush L1, L2 (Instruction and Data) cache and then begin my measurements.

Is it doable from user mode?

Processor: ARM Cortex A9

OS: Linaro Linux

ARMv7A family members will have PMU on the processor. Using this PMU, we can access cycle counts. Can we relay on this using the simulator?

i am seeing an issue while doing Dhrystone test. i am using Dhrstone source code of version 2.1.

when i run this source code on LINUX platform, i got DMIPS/MHz =1.6

but there are some printing commands that prints variables used, when i disable them i got…

Hello,

Consider following scenario:

1. A 4 KB page starting @0x80000000 is marked as Normal Memory, Inner Cacheable, write-back, non-shareable, non-outer cacheable, L2 is inclusive cache.
2. Now, the s/w writes to the first word in the page. Let's assume valid…