Hi everybody!!
I have a question on how get cache size on ARM v7-A, more specifically on A9 (or A7 or A15).
In accordance with the TRM at page 1529 I get the value from CSSIDR register and I compute the cache size. More precisely, I do cache size = num…
Hi all,
I'm trying to boot Linux on my hypervisor like environment.
In booting process, unexpected hyper trap was occurred and became hyp mode.
In hyp mode, the Hyp Syndrome Register (HSR) value is 0x93830006.
According to the manual, this meant "Fault…
what are the minimum hardware requirements to setup wifi on arm-7 processors.
What can be accessed by MRS/MSR in user mode?
In ARMv7-A/R ARM there is an encoding for ARMv7VE (A1):
| B9.3.10 | MSR (Banked register) |
| cond | 0 0 0 1 0 R 0 0 | M1 … |
I've beem constructing a list of Cortex-A7 ARM-instructions, and there are some questions I haven't found
an answer to in ARMv7-A/R ARM Issue C.
How is this special?
| LDRD<c>_<Rt>,_<Rt2>,_<label>_LDRD<c>_<Rt>,_<Rt2>,_[PC,_#-0]_Special_case… |
When two clusters(Big/Little) exist in SoC, the timer can be used to support Synchronization between two clusters.
But How to understand "Synchronization", anybody can tell me some typical application context? I am really confused......
And, if…
Is there a reason why banked registers SP and LR can't be accessed as r13_<mode> or r14_<mode>, but
one has to use SP_<mode> or LR_<mode> instead? It makes macros and inline assembly difficult.
In document (ARMv7-A/R ARM Issue…
Just in case someone needs them, I made ARM and Thumb mode lists of Cortex-A7 instructions (because I didn't find them in the net).
They are generated from ARMv7-A/R ARM with a simple AWK-script and then edited, so they may contain errors.
The lists…
Does anyone know if there is a list of ARM instruction set pseudo instructions?
Or better yet, an instruction list like PPC's, where there is a list of 'true instructions' with mnemonics and
another list of "simplified mnemonics" (=pseudo instructions…
Now that the funny PABT-behaviour is found to be (probably) caused ny debug state, I'd like to exit debug state before return from PABT exception. The ARM v7-A/R ARM says that I should write RRQ to DBGDRCR, but it seems that in Cortex-A7 it's not accessible…
I'm doing some testing on Exynos5422 SoC which implements big.LITTLE architecture (A7 + A15), I'm running bare metal application which starts in HYP mode. I haven't returned from HYP mode by accident and then software delay which I implemented by simple…
Hi !
Consider a micro-kernel (not Linux) where device drivers are userland applications (PL0).
We would like to use DMA based device, like an Ethernet controller for example. To this mean, the micro kernel allocate some memory to the user application…
Hello Guys,
Please refer below attached image. as shown in this image i want to measure the different latencies in my Trustzone based application.
Here is the list of measurements which i want to perform.
1) FIQ latency when RTOS runs and FIQ occurs …
I use a Cortex-A7 board and write start up code.
I try to use Security Extension.
I use `smc` instruction and make cpu mode monitor mode.
In the monitor handler, I tried to changed stack pointer value for calling other functions.
But after execute `ldr sp…
The ARM Cortex-A mobile application processor product line spans several generations and three main product tiers. Developers and SoC designers experienced with one or more of the newer ARM ARM Processors benefit from an…
A question that I am asked many times is – what is the fundamental difference between the high efficiency, mid range and the high performance application processors in the ARM Cortex family?
The simple answer to this is – the power budget…
The ARM Cortex-A7 MPCore processor is the most energy efficient application processor that ARM has ever developed and has dramatically extended ARM’s low-power leadership in entry level smart phones, tablets and other high end mobile devices. Here…
An excellent whitepaper that describes the features of Cortex-A7 and applications of this little processor.
This white paper describes in detail the design choices considered including choice of feature set and performance level, and how its simplified…
