Secure SPI : STM32MP157-DK1 board

Simon

Hey everyone,

I am working on STM32MP157-DK1 with trustzone cortex-A.
I want to use the SPI in secure side, but it's possible only with SPI 6 that is not mapped to the outside.

It's possible to activate SPI (1 ... 5) peripherals in secure side ? if…

Running two bare-metal programs on two separate cores in Cortex-A9

Adeeljs

Hello,

I have run two different bare-metal programs on two corresponding ARM cores in Cyclone V (Cortex-A9) in DS5 using JTAG line. The SDRAM is shared between the two cores as is evident from the cache settings which is set to "shared" by default. Core…

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Arm Cortex-A8 program flow prediction

alireza11048

I am examining ARM-Cortex A8 flow prediction abilities, in order to done this i implemented below code:

char SecretDispatcher[256 * 512];
int counter = 0;

//evicting SecretDispatcher from cache
...

while(counter < (512 * 9 + 1))
{
    //evict…

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What is the difference between ARM cortex-A and cores in snapdragon from Qualcomm?

Nitin Bhaskar

Hi All,

What is the difference between ARM cortex-A and cores in snapdragon from Qualcomm? I know that they say it is compatible with ARMv7/8 ISA.

Regards

Nitin

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ARMv7-A: What is "Fault not on a stage 2 translation for a stage 1 translation table walk"?

Takumi Shimada

Hi all,

I'm trying to boot Linux on my hypervisor like environment.

In booting process, unexpected hyper trap was occurred and became hyp mode.

In hyp mode, the Hyp Syndrome Register (HSR) value is 0x93830006.

According to the manual, this meant "Fault…

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Where is hardware interrupt latency documented for the ARMv8 Cortex-A53?

Tracy Smith

Need specific references to the hardware interrupt latency for the ARMv8 Cortex-A53. interrupt latency from when an interrupt is triggered to when the ISR is initially invoked, but not including operating system, kernel, or application latency.

…

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cortex-A15 instruction set and optimization ways on this platform?

Meng

Dear,

I am an greenhand developer on cortex-a15.

now I need some specification as follows:

where I can get the instruction set of cortex-A15?

are there some documents about optimization technology on cortex-A15(image processing optimization)

Thanks a lot.

…

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Is the single or multicore Cortex-A5 suitable for the Mali500 and Mali550?

dudu8

There is no cortex-A5 in the related products tab.

Mali-V550 - ARM

Why does FPU performance differ in AArch64 and AArch32 with Cortex-A53?

Yasuhiko Koumoto

Hello experts,

I have come to having a question.
VFP Benchmark is a benchmark application which was made by a certain Japanese in order to measure ARM VFP performance especially for ARMv7-A and ARMv8-A.
The software can be downloaded from the following link…

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Cortex A code / function alignment

Vincent Siles

Hi !

I am writing assembly code for some ARMv7a and ARMv8a CPU. I know that code has to be 4 bytes aligned, but I saw in several places (uboot/linux) the ".align 4" GCC directive, which will align to 2**4 = 16 bytes.

When writing code that will…

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8-byte stack alignment for ARM Cortex-A9

Holger Elsenheimer

Hello everbody,

as i have written before in "Compability between architecture ARMv5TE and ARMv7-A", we want to change our Platform-Processor from ARM946E-S to an ARM Cortex-A9. The next Point in our risk disclosure ist the stack alignment.

Our…

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Why I can't find the performance monitoring event for all Instructions count? How to get instructions event for my ARMV7 Cortex-A9 by PMU?

hello_arm

Can anyone help?

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De-merits in using Cortex A9 for single core processor

techguyz

Hi Experts,

A8 is meant for single core and A9 is for multi-core based.

Consider in case of SoC is build with single core of A9 and A8 how we could compare both in terms of some metrics/parameters like power/speed ?

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updating CPSR in USER UNPRIVILEGED mode

anoop

as we know supervisor mode is priviliged and user is not. at reset time in debugging mode, i read the cpsr it is 0x1d3 means in supervisor mode, so i can change CPSR so i changed it to 0x1d0 which is user mode, since user mode is unpriviliged so i must…

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STREX always clears the exclusive access tag

Gustavo A. R. Silva

Hello everybody,

Section 18.8 Exclusive access of Cortex-A Series Programmer's Guide says the following:

STREX can be considered as a conditional store. The store is performed only if the physical address is still marked as exclusive access (this means…

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code compile using -mcpu for ARM platform

Jay Zhao

When using gcc to compile c code for ARM platform, we set object platform by using:

-mcpu = xxxxxx

To what extent will that affect results of compiling ?

For example:

-mcpu = cortex-a8

and

-mcpu = cortex…

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The merit of data cache cleaning

Henry Choi

Hello everyone, my 1st question to the ARM community; please excuse my ignorance. Fairly recently, I shared OCM (on-chip-memory) on Xilinx Zynq processor (which is dual ARM Cortex A9). To pass message between the 2 cores, I followed the Xilinx example…

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system requirements

SGR

what are the minimum hardware requirements to setup wifi on arm-7 processors.

MRS/MSR (Banked register)

Juha Aaltonen

What can be accessed by MRS/MSR in user mode?

In ARMv7-A/R ARM there is an encoding for ARMv7VE (A1):

B9.3.10

MSR (Banked register)

cond

0 0 0 1 0 R 0 0

M1 …

Answered

Cortex-A9/GIC: de-activate an active interrupt

42Bastian

Hi

my situation: Running an OS in normal-world which due to an (user) error enters safe state with interrupts disabled. The Hypervisor enters by an FIQ (watchdog) and should reset the normal-world.

No the problem: If the normal-world error happens in an…

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Dhrystone Testing on Cortex A9: disabling Prints increases the DMIPS.

anoop

i am seeing an issue while doing Dhrystone test. i am using Dhrstone source code of version 2.1.

when i run this source code on LINUX platform, i got DMIPS/MHz =1.6

but there are some printing commands that prints variables used, when i disable them i got…

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Still more stupid questions on Cortex-A7 instruction set

Juha Aaltonen

I've beem constructing a list of Cortex-A7 ARM-instructions, and there are some questions I haven't found

an answer to in ARMv7-A/R ARM Issue C.

How is this special?

LDRD<c>_<Rt>,_<Rt2>,_<label>_LDRD<c>_<Rt>,_<Rt2>,_[PC,_#-0]_Special_case…

Questions about Generic Timer in ARMv8

wangchj

When two clusters(Big/Little) exist in SoC, the timer can be used to support Synchronization between two clusters.

But How to understand "Synchronization", anybody can tell me some typical application context? I am really confused......

And, if…

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ARM Context ID Register & Process Context Switch

onion

Hi, all

What is the content of Context ID Register of ARM Cortex A9. Is it OS that is responsible for assigning the value

of Process ID and ASID? As far as I know, it is so in Linux. Is that the same in the other OSes?

Is it essential to deal with ASID if…

Funny asymmetry with banked register names

Juha Aaltonen

Is there a reason why banked registers SP and LR can't be accessed as r13_<mode> or r14_<mode>, but

one has to use SP_<mode> or LR_<mode> instead? It makes macros and inline assembly difficult.

In document (ARMv7-A/R ARM Issue…

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