Arm Cortex-A8 program flow prediction

alireza11048

I am examining ARM-Cortex A8 flow prediction abilities, in order to done this i implemented below code:

char SecretDispatcher[256 * 512];
int counter = 0;

//evicting SecretDispatcher from cache
...

while(counter < (512 * 9 + 1))
{
    //evict…

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How get ARMv7 cache size

John

Hi everybody!!

I have a question on how get cache size on ARM v7-A, more specifically on A9 (or A7 or A15).

In accordance with the TRM at page 1529 I get the value from CSSIDR register and I compute the cache size. More precisely, I do cache size = num…

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MMU deactivation and I-Cache / Branch Predictor

Vincent Siles

Hi !

In order to call some functionality hard-coded in my board ROM (HAB from NXP i.MX6 board), I need to shut down the MMU: the ROM is not position independent. In particular, it is not always possible to map it and the devices correctly due to restriction…

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Can anyone provide an example of asynchronous exceptions?

Jay Zhao

Below is from ARMv7 Architecture doc.

An exception is described as asynchronous if either of the following applies:
— the exception is not generated as a result of direct execution or attempted…

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The merit of data cache cleaning

Henry Choi

Hello everyone, my 1st question to the ARM community; please excuse my ignorance. Fairly recently, I shared OCM (on-chip-memory) on Xilinx Zynq processor (which is dual ARM Cortex A9). To pass message between the 2 cores, I followed the Xilinx example…

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About PL310 cache controller and data aborts

Niranjan Dighe

Hello All,

I am working on a automotive product based on i.MX6q and recently facing an issue where we see kernel error with message "imprecise external abort". I am trying to analyze it and need to know a few things (which are not very clear in the TRM…

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Memory barrier (DSB, DMB). Does they guarantee writing data on cache to memory?

Yeo Reum Yun

Hi Experts,

I'm reading white paper for ARMv7 and ARMv8.

but when i reading cache part and memory re-ordering, i have silly questions.....

Suppose there are below instructions..

Core A:

STR R0, [Msg]

STR R1, [Something…

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Feature wise comparision for Cortex A series processors

techguyz

Hi Experts,

Is there any document on feature wise comparison chart on the Cortex A series of processors ?

Like,

Cache for Cortex A8/9/52...

MMU for cortex A8/9/52..

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ARM Cortex A9 flush cache

Tamilselvan Shanmugam

I'm measuring worst case execution time of an application. I would like to flush L1, L2 (Instruction and Data) cache and then begin my measurements.

Is it doable from user mode?

Processor: ARM Cortex A9

OS: Linaro Linux

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ARMv7 CortexA9 Cache Policy - No allocate ?

josecm

I was wondering if it would be possible to configure cache policy in the page table entry (short descriptor format) in such a way that the cache is used only if the data already exists in the cache? A kind of write-through / "no-allocate" policy?…

Data synchronization Barrier and cache.

Marcin.Kondraciuk@secom.com.pl

Hi, everybody. I have system based on multiprocessors system with ARMv7-A. I need copy table from one point of memory to another. I use for this task DMA. Memory attribute is write-back cacheable. Before starting copy by DMA, I clean data cache by MVA…

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Armv7 Store Buffer

Yang Wang

Hi,

Store Buffer holds store operation before it is commited to Cache or Main Memory.

So only if the proper store buffer entry is drained, can we get the right data by a load operation. Am I right?

If yes, is it possible that we read a unexpected value…

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Cortex-A9: Eviction of dirty line from the region marked as Only "Inner Cacheable" from L1 cache - will if be allocated into L2?

Hemant

Hello,

Consider following scenario:

A 4 KB page starting @0x80000000 is marked as Normal Memory, Inner Cacheable, write-back, non-shareable, non-outer cacheable, L2 is inclusive cache.
Now, the s/w writes to the first word in the page. Let's assume valid…

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