Greetings,

I'm currently experimenting with Jekyll and I'm trying to make an GNU ARM Assembly syntax highlighter for Rouge.

However, the ARM Architecture Reference Manual does not seem to have a simple complete list of mnemonics. They are all…

Hi !

In order to call some functionality hard-coded in my board ROM (HAB from NXP i.MX6 board), I need to shut down the MMU: the ROM is not position independent. In particular, it is not always possible to map it and the devices correctly due to restriction…

would u mind telling me please I'm really interested in this kind of stuffs.

Hello everybody,

Section 18.8 Exclusive access of Cortex-A Series Programmer's Guide says the following:

STREX can be considered as a conditional store. The store is performed only if the physical address is still marked as exclusive access (this means…

Dear all,

I am interested in a scenario where I want to host two guest OSes above a bare-metal hypervisor on an ARM mobile platform. The total available memory platform is 4GB where I want to expose exclusively 2 GB of continuous RAM to each guest OS.…

What does it mean that an instruction is a hint instruction, like NOP, YIELD and WFE?

I haven't found any explanations in ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition, Issue C.

[EDIT]

Aha, this has already been answered in:

Are…

What can be accessed by MRS/MSR in user mode?

In ARMv7-A/R ARM there is an encoding for ARMv7VE (A1):

Any idea about instructions marked as UNPREDICTABLE: can it then be UNDEFINED?

In other words: UNDEFINED REQUIRES the instruction to cause UND-exception, but

MAY UNPREDICTABLE do that, or does it have to execute normally except that the result may be…

I've beem constructing a list of Cortex-A7 ARM-instructions, and there are some questions I haven't found

an answer to in ARMv7-A/R ARM Issue C.

How is this special?

In the ARMv7-A/R ARM Issue C I found two instructions with odd encoding: PUSH and POP, encoding A2.

What's the Rt's role? I guess Rt and 'registers'-bitlist needs to match?

Encoding A2 ARMv4*, ARMv5T*, ARMv6*, ARMv7

PUSH<c> <registers>…

For ARMv7 -A/R systems, the MMU uses an ASID to distinguish between memory pages which have the same virtual address, but which are used by an individual task ( I.e. A task which uses non-Global memory). The ASID is an eight-bit value, from 0-255, assigned…

Is it

MOVS pc, r14

or

SUBS pc, r14, #4

This is written in the ARMDEN0013D. but in the table it says next instruction whereas the SUBS pc, r14, #4 means the instruction which was interrupted.

From the CPU's point of view, how does it distinguish an assembly code is an ARM code or a Thumb code?

Is there some signal bit represent the code is ARM or Thumb code, this is just my guess.

Hello,

I want to benchmark my program running on Linux on an Altera Cyclone V SoC board, but it turns out that the values returned from the ARM Cortex-A9 PMU cycle counter suggest that some sort of CPU frequency scaling is active, which is confusing me…

Hi ARM expert,

    In ARM V7 RM, I saw "This chapter describes the implementation of the ARM Generic Timer as an OPTIONAL extension to an ARMv7-A or ARMv7-R processor implementation.". So, I think it means that a SoC implementation…

range of BL instruction in arm state is + or - 32MB as per instruction set.how...........?