Spin-lock implementation for Aarch64 -- how to enforce acquire semantics?

Olivier Delande

Here is a minimal C implementation of a spinlock "lock" operation using GCC's built-in atomics:

#include <stdbool.h>

void spin_lock(bool *l) {
  while (__atomic_test_and_set(l, __ATOMIC_ACQUIRE))
    ;
}

I am concerned…

Answered

float behaivior on AARCH64

Christian Dreihsig

Hello,

forgive me if my question is a litte bit weak in content and linguistic. I'm only a Hobbyist and english is not my nativ.

I'm trying to compile an App from Einstein@Home for AARCH64 using GCC. Einstein@Home is a DC-Projekt using Boinc. The App…

Answered

Why does FPU performance differ in AArch64 and AArch32 with Cortex-A53?

Yasuhiko Koumoto

Hello experts,

I have come to having a question.
VFP Benchmark is a benchmark application which was made by a certain Japanese in order to measure ARM VFP performance especially for ARMv7-A and ARMv8-A.
The software can be downloaded from the following link…

Answered

shareable attribute in armv8

Harish G

Hi Experts,

I was going through the arm v8 mmu page table formation, when it's compared to arm v7 it is completely different.

I could…

Answered

indicator for A core system timer implemented or not

hostia

Hi ARM expert,

In ARM V7 RM, I saw "This chapter describes the implementation of the ARM Generic Timer as an OPTIONAL extension to an ARMv7-A or ARMv7-R processor implementation.". So, I think it means that a SoC implementation…

Answered

VMSAv8-64 -- worst-case effects of misprogramming of the Contiguous bit

Olivier Delande

I would like to precisely understand the implications of misprogramming the Contiguous bit in VMSAv8-64 translation tables.

I have a hypervisor running at EL2 in the AArch64 execution state, using two-stage memory translation for the guests. At some point…

Correct usage of the NSTable bit in aarch64/armv7a LPAE

Vincent Siles

I'm porting our armv7a-short descriptor OS to LPAE and aarch64. In the short descriptor MMU, the "NS" bit can only be found in the first level of the MMU (I'll call it the SECTION level), meaning that only a single page cannot be tagged as NS, a whole…

Answered

aarch64 kernel using aarch32 page tables

Vincent Siles

Hi !

I'm trying to update my custom kernel, working with short or long descriptor in armv7a to a target supporting armv8.

My current setup uses TTBR0 to point to the PL0 page table and TTBR1 to point to the PL1 page table.

At the moment, I sometimes…

Answered

A question about the access flag fault

zhaoshijun

Hi, everyone.

The CPU will receive a access flag fault if we set the access flag = 0. My question is if we always set the access flag to be zero in the fault handler, does the CPU get the value in the memory? For example, the instruction "ldr rd, address…

Answered

How to compile hello word code with aarch64 gcc

Huailiang Li

Assembly code:

    .syntax unified

    @ --------------------------------
.global main
main:
    @ Stack the return address (lr) in addition to a dummy register (ip) to
    @ keep the stack 8-byte aligned.
    push    {ip, lr}

    @ Load the…

ARM Shares Updated Cortex-A53/A57 Performance Expectations

wangyong

With the first Cortex-A53 based SoCs due to ship in the coming months, and Cortex-A57 based designs to follow early next year, ARM gave us a quick update on performance expectations for both cores. Given the timing of both designs we'll see a combination…

over 6 years ago
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