• Why does FPU performance differ in AArch64 and AArch32 with Cortex-A53?

    Yasuhiko Koumoto
    Yasuhiko Koumoto

    Hello experts,


    I have come to having a question.
    VFP Benchmark is a benchmark application which was made by a certain Japanese in order to measure ARM VFP performance especially for ARMv7-A and ARMv8-A.
    The software can be downloaded from the following link…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Is there a list of all opcodes mnemonics understood by each architecture?

    Myy
    Myy

    Greetings,

    I'm currently experimenting with Jekyll and I'm trying to make an GNU ARM Assembly syntax highlighter for Rouge.

    However, the ARM Architecture Reference Manual does not seem to have a simple complete list of mnemonics. They are all…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex A code / function alignment

    Vincent Siles
    Vincent Siles

    Hi !

    I am writing assembly code for some ARMv7a and ARMv8a CPU. I know that code has to be 4 bytes aligned, but I saw in several places (uboot/linux) the ".align 4" GCC directive, which will align to 2**4 = 16 bytes.

    When writing code that will…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARMv8 Secure EL1 problem

    Steven Meng
    Steven Meng

    Hi, arm experts,

    We want to use ARCH32 mode in secure EL1, I see some descriptions in ARMv8 Arch Reference Manual about Secure EL1 ARCH32 mode as follows:

    One is the VBAR(secure), it is mapped to  VBAR_EL3, the other is SCTLR (secure), it is mapped to …

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • indicator for A core system timer implemented or not

    hostia
    hostia

    Hi ARM expert,

        In ARM V7 RM, I saw "This chapter describes the implementation of the ARM Generic Timer as an OPTIONAL extension to an ARMv7-A or ARMv7-R processor implementation.". So, I think it means that a SoC implementation…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • aarch64 kernel using aarch32 page tables

    Vincent Siles
    Vincent Siles

    Hi !

    I'm trying to update my custom kernel, working with short or long descriptor in armv7a to a target supporting armv8.

    My current setup uses TTBR0 to point to the PL0 page table and TTBR1 to point to the PL1 page table.

    At the moment, I sometimes…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • A question about the access flag fault

    zhaoshijun
    zhaoshijun

    Hi, everyone.

     

    The CPU will receive a access flag fault if we set the access flag = 0. My question is  if we always set the access flag to be zero in the fault handler, does the CPU get the value in the memory? For example, the instruction "ldr rd, address…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM v7 Instruction Set Architecture Opcode Code

    DavidSV2017
    DavidSV2017

    Hello,

    I am working with some ARM hardware and I wrote a program in ARM Assembly. The ARM hardware that I am using requires the the program to be in HEX values and I found a website online that allowed me to convert the ARM Assembly language to HEX, the…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum