I'm reading "ARM® Cortex®-A53 MPCore Processor Technical Reference Manual".

And, in 6.7 Direct access to internal memory part (P.357), there is a problem to understand what is the meaning of AArch64 register 'Operation' part.…

Hey i have question. 

I have a problem with execution of program (64-bit) I'ts a bioinformatic program (http://ffas.sanfordburnham.org/ffas-cgi/cgi/download.pl?ses=&rv=&lv= [with source code]) I building a cluster of 5x orange pi one plus (

Hi,

I'm trying to enable PMU's on arm versatile juno r2 development board.

I've already read this manuals from arm:
ARM ® Cortex ® -A72 MPCore Processor
ARM® Cortex ® -A53 MPCore Processor
Juno r2 ARM® Development Platform SoC…

Hi ,

Please I need help, I need to download Eclipse in My board DE1-Soc FPGA Which has the latest dual-core Cortex-A9 embedded cores with architecture armv7l and the other board Rasberry ARM Cortex-A53.

do you have any idea which packages can I install…

Hi all,

I am trying to use the ETM on iMX53 qsb, which contains a Cortex-A8 processor. In the board, the trace result of the ETM is outputted to both ETB and TPIU via an ATB replicator, looks like the following figure,

I am going to enable the ETM and…

Hi,

I am trying to compile PMU Cycle Counter  as per  the code available in this blog PMU Enable on a RPI3 B+ using Suse 64 bits Aarch 64 4.12.14-lp150.12.28-default.

I have the Assembly error on each MRC or MCR instructions. In the ARM i have the feeling…

So I have worked with Arm 32 bit and was able to generate the log file which contains all the instructions and addresses and all... Now i want to do the same for 64 bit. But it seems we need another compiler to do the same. If possible, can you guys give…

Root of Trust implementation – Connected devices with authentication requirements need a root of trust in the system architecture. This is particularly important for devices that can be updated over the air. In a system with TrustZone technology, code…

Hi,

I am new to the ARM TrustZone Architecture.

I am confused that who sets the NS bit in the SCR register, is it the processor itself set bit to 1 when it enters the EL3 mode, or it is the Monitor mode code is setting the NS bit ?

Maybe I am asking…

From "ARM v8-M Architecture Reference Manual", about IDAU I see:

The IDAU can provide the following Security attribution information for an address:
• Security attribution exempt. This specifies that the address is exempt from security attribution…

Hi guys,

I found in armv8-arch ref manual that when PRIS bit in the AIRCR is set, the priority of non-secure handler is mapped to the bottom of the priority range. So I did an experiment.

I configured two exceptions, systick and svc. The priority are 2…

Hello All,

Requirements:

1. Write a secure program where some part of the program resides in a secure zone.
2. Code instrumentation: I would like to instrument the compiled binary that runs on the device 

I could find some options, however, I cannot differentiate…

Hi.

How do I start with simple example for study about boot rom and boot sequence?

I'd like to make a simple architecture, but first of all, I have to make a L1 boot and L2 Boot code as I know.

CM3 is connected with boot ROM and Flash.

So Would you…