• Optimizing code for ARM: ARMv7, ARMv8, Memory Models and NEON Intrinsics

    Matthew Du Puy
    Matthew Du Puy

    Matthew Gretton-Dann titled this presentation: Porting & Optimising Code 32-bit to 64-bit

    The title is accurate but he does a better job of giving a high level overview of the ARMv7 and ARMv8 architecture differences, C++11 memory models (which become…

    • over 6 years ago
    • Open Source Software and Platforms
    • Android forum
  • A couple of use cases for TrustZone for ARMv8-M

    Diya Soubra
    Diya Soubra

    Root of Trust implementation – Connected devices with authentication requirements need a root of trust in the system architecture. This is particularly important for devices that can be updated over the air. In a system with TrustZone technology, code…

    • over 3 years ago
    • TrustZone for Armv8-M
    • TrustZone for Armv8-M forum
  • Which component set the NS bit in SCR ?

    Sahil
    Sahil

    Hi,

    I am new to the ARM TrustZone Architecture.

    I am confused that who sets the NS bit in the SCR register, is it the processor itself set bit to 1 when it enters the EL3 mode, or it is the Monitor mode code is setting the NS bit ?

    Maybe I am asking…

    • Answered
    • over 3 years ago
    • TrustZone for Armv8-M
    • TrustZone for Armv8-M forum
  • Platform security architecture is announced by Arm

    Diya Soubra
    Diya Soubra

    • over 2 years ago
    • TrustZone for Armv8-M
    • TrustZone for Armv8-M forum
  • Given an address, how to check its IDAU Security attribution information?

    Tao Lu
    Tao Lu

    From "ARM v8-M Architecture Reference Manual", about IDAU I see:

    The IDAU can provide the following Security attribution information for an address:
    • Security attribution exempt. This specifies that the address is exempt from security attribution…

    • Answered
    • over 1 year ago
    • TrustZone for Armv8-M
    • TrustZone for Armv8-M forum
  • A question about interrupt priority degrade

    Wenchuan2018
    Wenchuan2018

    Hi guys,

    I found in armv8-arch ref manual that when PRIS bit in the AIRCR is set, the priority of non-secure handler is mapped to the bottom of the priority range. So I did an experiment.

    I configured two exceptions, systick and svc. The priority are 2…

    • Answered
    • over 1 year ago
    • TrustZone for Armv8-M
    • TrustZone for Armv8-M forum
  • Development platforms, compilers for TrustZone

    Seema
    Seema

    Hello All,

    Requirements:

    1. Write a secure program where some part of the program resides in a secure zone.
    2. Code instrumentation: I would like to instrument the compiled binary that runs on the device 

    I could find some options, however, I cannot differentiate…

    • Answered
    • over 1 year ago
    • TrustZone for Armv8-M
    • TrustZone for Armv8-M forum
  • New online training course – An Introduction to Armv8-M

    Joel Eaton
    Joel Eaton

    We are very pleased to announce a new online training topic – An Introduction to Armv8-M.

    This is the latest addition to our introduction to Arm the Arm architecture series and is targeted to those new to developing on Armv8-M or those wanting a…

    • over 2 years ago
    • Processors
    • Processors blog
  • Whitepaper - ARMv8-M Architecture Technical Overview

    Joseph Yiu
    Joseph Yiu

    The next generation of ARM Cortex-M processors will be powered by a new architecture version called ARMv8-M architecture. This document provides a technical overview of various enhancements in the new architecture, as well as an introduction to the security…

    • Whitepaper - ARMv8-M Architecture Technical Overview.pdf
    • over 3 years ago
    • Processors
    • Processors blog