Hi,
When core makes a transaction, NS signal is sent on AXI bus depending on the SCR.NS bit.
But when DMA transaction is issued, how the NS bit is propagated on the AXI bus ?
Thanks
Sahil
Hi,
When core makes a transaction, NS signal is sent on AXI bus depending on the SCR.NS bit.
But when DMA transaction is issued, how the NS bit is propagated on the AXI bus ?
Thanks
Sahil
I have read in one ARM document
The TrustZone Address Space Controller (TZASC) is an AXI component which partitions its slave address range into a number of memory regions. The TZASC can be programmed by Secure software to configure these regions as Secure…
We know that chip designers can use an Implementation Defined Attribution Unit (IDAU) to define a fixed memory map. A region can be defined as Secure,
Non-secure, or Exempt.
If SAU_CTRL ENABLE bit is set as 0, and the ALLNS bit is set as 1, then all memory…
This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.
This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.
This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.
This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.
This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.
This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.
This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.
This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”
Hi,
I am just performing the first steps with the DesignStart Eval Edition (Cortex-M0), trying to compile the verilog sources to get a simulation running.
So I changed /systems/fpga_testbench/trl_sim/makefile to use gcc and modelsim and now I want to …
Hello,
I am new to AXI. Where should I lookout for information on awcache signal. The protocol has various cache transfers. What is the difference between each of them? Where can I lookout for this information?
My input is AHB while output is AXI.
AHB…
Hi,
I'd like to try and use external BRAM as the I/D memory for the Cortex-M1 DesignStart package for Xilinx FPGAs. The reference examples for Arty boards use the internal TCMs.
I've built a design in Vivado with a BRAM connected to the AXI3 port mapped…
Hello all,
I have 2 questions regarding the Cortex M IP cores for Xilinx FPGAs (M1 on the Arty A7/S7, provided by ARM)
1) I am new to ARM DesignStart and am looking to use freeRTOS with the Cortex M1 which project which has been provided for the Arty A7…
Hi. First of all, thanks for your attention in advance. I have to say that I am completely new in FPGA programming, but I could have never imagined that running an example with a documentation explaining it step by step could be so cumbersome and error…
Hello,
I have already played around with the Cortex-M1 reference designs for Xilinx Spartan and Artix boards, can you give an indication of what your maximum target frequency for the processor IP core is? Are the referenced 100 MHz a good design practice…
I'm trying to load the block diagram for the arty a7 M1 example project. I get this error:
[BD 41-1712] The specified IP 'xilinx.com:ip:axi_bram_ctrl:4.0' does not support the current part 'xc7a35ticsg324-1L'
Any thoughts on how to…
Dear Forum,
Can you please confirm one thing.
When we have un-aligned transfer, do some of WDATA bits not used during that transfer?
For example, in the below unaligned transfer WDATA[7:0] are not used for the 1st transfer. Is my understanding right?
…Hi Forum,
I cannot understand when address is being wrapped in WRAP burst.In my example, the WRAP condition never happens in other words, during BURST operation address always remains small than wrap address.
From the spec, the wrapping happens when
…How do you confirm if a slave is sampling on positive edge of clock only ? How can we prove this in simulation
Hi,
I am aware that like other channels, the handshaking signals of the Write Response can assert in any order (that means BVALID and BREADY can assert either together at the same clock edge of one after the other in both the orders). But is there any…
Hi,
I am creating a systemC model for a peripheral which has an AXI4 interface.
Is there a bit and pin accurate AXI4 SystemC model similar to the ones available for OCP?
Is it available from ARM, a ThirdParty vendor, or the opensource community?
I am new to AXI4 protocol. I would like to know how many clock cycles are required to complete a AXI4 burst write transaction.
Eg. Burst length- Two , Burst size 16 bytes.
Please give me answers for different types of data bus width say for bus width …