• Transfer size in AMBA AXI

    subhajit02
    subhajit02

    Hi, I am not so clear about the concept of transfer size in AMBA AXI. My question is how to calculate wrap_boundary in wrap based data transfer when Number_Bytes (The maximum number of bytes in each data transfer) is changing in each transfer within a…

    • over 3 years ago
    • System
    • Embedded forum
  • AXI-4 questions

    SBR_123
    SBR_123

    Hello,

    I am pretty new to AMBA protocol and I am specifically interested in AXI-4. I have a few fundamental questions related to AXI-4 and I would appreciate if anyone can answer these.

    1) I would like to know how read and write address requests issued…

    • Answered
    • over 4 years ago
    • System
    • Embedded forum
  • RE: In read or write transaction in AXI.what happen if data transaction  is before address.

    Mayank
    Mayank

    Hii,

    In AXI 3 if  data items are written before the address comes due to register delays .....then where that data is being stored in memory because no address is being specified till now...?

    please resolve this issue...

    Thanks 

    • over 3 years ago
    • System
    • Embedded forum
  • AXI4 Stream difference between Position Byte and Null Byte

    nishith
    nishith

    In AXI4 Stream protocol apart from data byte two other byte types are defined known as position byte and null byte. 

    For the position byte the description says: "A byte that indicates the relative positions of data bytes within the stream. This is a placeholder…

    • over 3 years ago
    • System
    • Embedded forum
  • burst-based transactions on AXI

    PJ_
    PJ_

    Hi,

    I'm confusing with burst transaction in AXI.


    there is one key feature in AXI spec....
    > "burst-based transactions with only start address issued"

    How can we understand this point?

    Thanks,

    • over 2 years ago
    • System
    • Embedded forum
  • pseudocode description of transfer in AXI

    rana
    rana

    Hello I am  new to AXI and just saw the pseudocode for a transfer in the spec of AXI . My question is regarding Data_Bus_Bytes .

    Q1-  The spec says that Data_Bus_Bytes is  number of 8 bit byte lanes in the bus. Is it same  as Number_Bytes which is 2^AWSIZE…

    • over 2 years ago
    • System
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  • Barrier Transactions in ACE

    Josesmn
    Josesmn

    Can somebody please explain how barrier transactions in ACE work?

    Thanks in advance.

    • Answered
    • over 2 years ago
    • System
    • Embedded forum
  • Write transfer in AXI3

    karukaka
    karukaka

    A master wants to initiate write transfers to two different slaves whose address ranges are consequtive   can he choose to initiate write transfer starting in 1st slave address range and choose ASIZE and ALEN such that second slave is also covered? if yes…

    • over 2 years ago
    • System
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  • AXI Wrap burst address calculation, start_addr=0x96h, burst_size=8transfers each of 4 bytes wide

    Tejashree
    Tejashree

    Hello,

    I am unable to understand , which start address should i take in case of wrapping burst address calculation of AXI?

    For example , 

    my Burst size=4 transfers(beats)

    each beat(transfer)size=4bytes=32bits.

    hence total size of burst=32*8=256bits. Hence…

    • over 2 years ago
    • System
    • Embedded forum
  • How to map tag RAM banks to data cache lines in Cortex-R5?

    Etienne Alepins
    Etienne Alepins

    Hi,

    We are using Cortex-R5F. Through the AXI slave interface, we are accessing the data cache data RAM, tag RAM and dirty RAM. We would like to know how we can associate the bits found in the data RAM with the bits found in the tag RAM. For example,…

    • over 2 years ago
    • System
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  • AXI read response in error case

    Anupam Jain
    Anupam Jain

    Hi,

    In the AXI spec it is mentioned that , even in case of ERROR response, the slave needs to respond with the exact number of beats and indicate the response with each beat.

    Now my question here is if the response is going to be ERROR(lets say SLVERR…

    • over 2 years ago
    • System
    • Embedded forum
  • Why AXI4 changed the definition of AxCACHE?

    Yu-Hsin
    Yu-Hsin

    Hi,

    In AXI4, spec changed the definition of the definition of AxCACHE[3:2] from Write Allocate/Read Allocate to be Allocate/Other Allocate.

    But is there any concrete reason for this change? Actually I found some related statements from spec, but I couldn…

    • over 2 years ago
    • System
    • Embedded forum
  • Store operations where the cache line is already cached (ACE protocol)

    Vedant2611
    Vedant2611

    In Section C1.3 Channel Overview of the AMBA_AXI_and_ACE protocol specifications, It is mentioned under "Store operations where the cache line is already cached" as :

    The initiating master component requests a unique copy of the cache line…

    • over 2 years ago
    • System
    • Embedded forum
  • Removal of WID's in AMBA AXI4

    mvenkatesh
    mvenkatesh

    Hi ,

       What is the purpose of removing ID's (WID) in AXI4 ?

    If it because of reduction of pin count then We lost the " Write Data Interleaving" and "Out Of Order " Transaction features. Can you please tell me if any other reasons...(Arm Spec says.…

    • over 2 years ago
    • System
    • Embedded forum
  • Xen/dom0 on Juno

    Justin
    Justin

    Hey all,

    I have been playing around with Xen and Dom0 on a Juno r0 board. Currently dom0 is failing to initailize USB. This is an issue because the rootfs depends on the usb.

    usb 1-1: new high-speed USB device number 2 using ehci-platform

    usb 1-1: device…

    • Answered
    • over 4 years ago
    • Open Source Software and Platforms
    • Arm Development Platforms forum
  • How does device access work in AEMv8 models?

    gungomanj
    gungomanj

    Hello everyone,

    I am questioning whether everything is set up through the VE system registers or if there's AXI / ACE emulation in these models. Thank you in advance!

    • over 3 years ago
    • Open Source Software and Platforms
    • Arm Development Platforms forum
  • Juno MSI support

    arnd
    arnd
    Hello,
    I am working with a Juno platform (r1 & r2) and I have a PCIe endpoint device connected that supports 32 MSIs. When the endpoint device driver tries to register these IRQs using devm_request_irq() the request fails with error code 22.
    Looking…
    • over 3 years ago
    • Open Source Software and Platforms
    • Arm Development Platforms forum
  • Issue while building the OpenEmbedded filesysytem from source (ARM Versatile Express Juno r2 Development Platform)

    luismartins
    luismartins

    Similar to this thread, i'm having some hard time building the openembedded filesystem.

    So far I have managed to follow this tutoriall until the "Booting the board" section. After running the board some errors appear during the execution:

    Execution of the PuTTY shell (Part 1)

    Execution of the PuTTY shell (Part 2)

    This…

    • Answered
    • over 2 years ago
    • Open Source Software and Platforms
    • Arm Development Platforms forum
  • ARM blue pill does not respond correctly

    MB.Pejvak
    MB.Pejvak

    I use blue pill ARM-based board and XBee module. the module should communicate with other Xbees and according to data received, do appropriate task. the code in one MC connected to a module is as follow:

    #include <XBee.h>
    #include <XBeeGenDef.h>
    #include…
    • over 2 years ago
    • Open Source Software and Platforms
    • Arm Development Platforms forum
  • AMBA Protocols (Specially AXI) frequency limit ?

    Smk417
    Smk417

    I wanted to ask about AMBA Protocols (Specially AXI) frequency limit ? Is there any upper limit for AXI4 of maximum operating frequency ? what is it ?

    • over 2 years ago
    • Open Source Software and Platforms
    • Arm Development Platforms forum
  • Partial Word Access to Altera Avalon Memory-Mapped Slave

    Qiangsheng Xiang
    Qiangsheng Xiang

    when I say partial word access, I mean 16-bit (two byte) or 8-bit (byte) read/write.

    Background:

    In one of our recent projects, Cyclone V SoC is used to replace 386 CPU in an existing product.

    I am responsible for the board and FPGA design. Another software…

    • Answered
    • over 5 years ago
    • System
    • SoC Design forum
  • why there is no split or retry responce in AXI ?

    Jay Zhao
    Jay Zhao

    In AHB, we have split and retry responce, but it doesn't exist in AXI, why ?

    • Answered
    • over 4 years ago
    • System
    • SoC Design forum
  • AXI narrow read with unaligned address

    jduarte
    jduarte

    Hi,

    I have a question about the correct behavior when performing a narrow read with an unaligned address; consider the following scenario:

    - 32 bit data bus

    - address x0001

    - length 0 (1 beat)

    - size 1 (2 byte)

    My interpretation of the spec is that in…

    • Answered
    • over 4 years ago
    • System
    • SoC Design forum
  • RMW operation on SRAM via AXI

    niket
    niket

    I am implementing Read Modified Write on SRAM through AXI. What is the role of awsize and wstrbe?

    Say data width is 64 bits, and awsize is set to support 64-bits, but the underlying wstrbe are only valid for lower 32-bits (8'b0000_1111). Does this candid…

    • Answered
    • over 4 years ago
    • System
    • SoC Design forum
  • AXI handshake between AW/AR-READY and B/R-RESP

    KalyanSuman
    KalyanSuman

    In AXI Write how the handshake between AW channel and B channel is taken care.

    Standard says that 

    "the slave must wait for both WVALID and WREADY to be asserted before asserting BVALID"

    Does that means BVALID will never be asserted in the same…

    • Answered
    • over 4 years ago
    • System
    • SoC Design forum
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