• AXI5: AtomicCompare transactions.

    raghav_rastogi
    raghav_rastogi

    Hi all,

    After reading the AXI5 specification, I ran into some doubts regarding the AWLEN of AtomicCompare transactions. As per the specification, we can have AWLEN > 0 which ultimately means we can have multiple beats for a particular transaction and…

    • 2 days ago
    • System
    • SoC Design forum
  • 求助ARM RealView ESL API v2.0 Developer's Guide中提到的C++文件和头文件在哪下载?

    newplayer
    newplayer

    • 1 month ago
    • 中文社区
    • 中文社区论区
  • AXI4 VIP unable to change values of control signal

    Rishu Kumar
    Rishu Kumar

    I'm using AXI VIP example design in Vivado 2020.1, 
    Can anyone here explain how can I setup AWVALID, AWREADY, ARVALID, ARREADY.


    My design is: AXI VIP master --> AXI Interconnect --> 4 BRAM controller --> 4 Single Port RAM (Block Memory Generator).…

    • 2 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Legal transactions for AXI FIXED mode

    Utkarsh S
    Utkarsh S

    Hello,

    I am currently using AXI with burst type of FIXED for writing into a fifo. its data bus width is 32 - bits.

    1. So i wanted to know whether AWSIZE of 64-bits and greater are legal or no. If it is legal then how should the data be stored in the fifo…

    • Answered
    • 5 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • AXI4 Bus Bandwidth/Data Transfer increase

    willo144
    willo144

    Hello,

    I am doing research with an Ultra-Embedded Implementation of a RISC-V Processor in gem5.  My team is using an Oracle Virtual Machine to run testbenches and benchmarks for our research motivation.  As part of our research, I have been tasked with…

    • 10 months ago
    • System
    • SoC Design forum
  • Getting started with AMBA and AMBA AXI

    NickT
    NickT

    As you may be aware, far from being a misspelled fossilized tree resin, AMBA is a freely available open standard for the connection and management of functional blocks in a system-on-chip (SoC). Since the mid-90s, AMBA has been implemented by vendors…

    • 11 months ago
    • Processors
    • Processors blog
  • AXI problem

    tom
    tom

    Hi All
    I have few questions about axi
    Q1:
    is it possible that WVALID , WREADY and BVALID assert at the same cycle?


    Q2: what is different between  out of order and data interleaving ?
    Q3: is it possible that  write transaction can happen all time in axi? i mea…

    • 11 months ago
    • DesignStart
    • DesignStart forum
  • AXI fixed burst to a slave with narrow data width

    Sana
    Sana

    Hi,

    I have an AXI master with data width 64, and an AHB slave of data width 32. What would happen when there is a 64bit FIXED burst READ (i.e., asize=3)to an address 0X100 of the slave? 

    Would the the data be read from 0x100 only, with data[63:32] always…

    • over 1 year ago
    • System
    • SoC Design forum
  • AMBA AXI Write response

    Sai Krishna
    Sai Krishna
    I am just going through the specs of AMBA AXI.
    I've few questions.It will be great if anybody clarify
    1) Why there was no Write response for each beat in burst Write. But there is a seperate Read response for each beat in a Read burst ?
    2) How to terminate…
    • over 7 years ago
    • System
    • SoC Design forum
  • applications of amba axi

    abilash abilash
    abilash abilash
    Note: This was originally posted on 7th February 2007 at http://forums.arm.com

    hello, i have read the whole of the axi protocol. i would like to know the applications of the protocol. is it anywhere used in the real time applications or some specific devices…
    • over 7 years ago
    • System
    • SoC Design forum
  • AXI write strobes

    jameskim jameskim
    jameskim jameskim
    Note: This was originally posted on 21st February 2007 at http://forums.arm.com

    the AXI spec says:

    10.1 About unaligned transfers
    [...]
    For any burst that is made up of data transfers wider than one byte, it is possible that the first bytes that have to be…
    • over 7 years ago
    • System
    • SoC Design forum
  • AXI Read/Write ordering

    Randy Pascarella
    Randy Pascarella
    Note: This was originally posted on 24th October 2007 at http://forums.arm.com

    Hello,
       Section 8.6 of the AXI spec says that reads and writes have no ordering restrictions between them.  It then says that if a RAW dependency exists, the master must wait…
    • over 7 years ago
    • System
    • SoC Design forum
  • More AXI write/read ordering

    Randy Pascarella
    Randy Pascarella
    Note: This was originally posted on 25th October 2007 at http://forums.arm.com

    In another posting, a scenario given was with a RAW hazard where a bufferable write was followed by a read to an overlapping address.  Sounds like the master's assumption upon…
    • over 7 years ago
    • System
    • SoC Design forum
  • AXI Cacheable vs. Bufferable

    Randy Pascarella
    Randy Pascarella
    Note: This was originally posted on 19th November 2007 at http://forums.arm.com

    If an AXI slave acting as a bridge has accepted a bufferable (ACACHE[0]) and cacheable (ACACHE[1]) write and responded with BRESP, is it required to flush this buffered write…
    • over 7 years ago
    • System
    • SoC Design forum
  • AXI protocol

    neha004
    neha004
    Note: This was originally posted on 30th December 2007 at http://forums.arm.com

    Can anyone tell me the exact explanation and differnce between out of order completion and write data interleaving  in detail...as i`m very confused with these terms
    • over 7 years ago
    • System
    • SoC Design forum
  • AXI locked access

    spark spark
    spark spark
    Note: This was originally posted on 29th May 2008 at http://forums.arm.com

    Does a locked request on either the read or write channel cause both channels to be locked? For example, one master request a locked write transaction to a slave, the read channel…
    • over 7 years ago
    • System
    • SoC Design forum
  • the usage of WSTRB signal

    Dong Luo
    Dong Luo
    Note: This was originally posted on 26th February 2009 at http://forums.arm.com

    Hi All,
    I was going through the AMBA AXI specs, but I have some questions about the usage of the WSTRB signal. In the middle of a burst, can some bits of WSTRB be low? Again…
    • over 7 years ago
    • System
    • SoC Design forum
  • Write Data Interleaving - AXI

    Amaresh Chaligeri
    Amaresh Chaligeri
    Note: This was originally posted on 19th March 2009 at http://forums.arm.com

    Hello,

    Can anybody help me to understand the reasoning behind write data interleaving ordering restriction imposed by AXI spec.
    [Chapter 8.5  Write data interleaving]

    "The order…
    • over 7 years ago
    • System
    • SoC Design forum
  • New Arm online training course: Introduction to the AMBA ACE protocol

    NickT
    NickT

    Arm is pleased to announce a new online training topic - An introduction to the AMBA ACE protocol.

    About the course

    This training topic covers essential information on Arm’s AMBA ACE protocol. Hardware system-level coherency enables the sharing of…

    • over 1 year ago
    • Processors
    • Processors blog
  • Aligned and unaligned word transfers on a 64-bit bus

    Maria_d
    Maria_d

    address = 0x07 

    transfer size = 32 bit

    burst type  = INC

    Burst length = 4 transfers

    Can you please explain this example of unaligned word transfer on 64-bit bus.

    Why the second transfer started at 8 and not from C?

    • over 1 year ago
    • System
    • SoC Design forum
  • Lock Signal for AXI Slave

    Tarun Mittal
    Tarun Mittal

    According to what I read in AXi spec sheet, AxLOCK signals are used by the Masters for a locked access to a slave and it's the arbiter/interconnect which takes care of the AxLOCK signal.
    Am I right when I say that, "Slave doesn't care if it's Locked…

    • over 1 year ago
    • System
    • SoC Design forum
  • AXI SLAVE PERIPHERAL

    Antonio
    Antonio

    Hi everyone! Please help me.. i have  a project with a custom axi slave  design that  implements multiple memory ranges 256 words each . A master ( my processor in figure) can write burst data to the example slave and read the data back. The problem is…

    • Answered
    • over 7 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • What is real application of Exclusive access in AXI

    Koteswara Rao P
    Koteswara Rao P

    Hi,

      What is real time application of AXI exclusive access.

      Is it necessarily to do Exclusive read first then exclusive write.

      May i know the reason is it so?

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Question about AXI Wrapping burst

    evelyn716
    evelyn716

    There is a statement 'For wrapping burst, the length of the burst must be 2,4,8 or 16 transfers.' in AXI Addressing option.

    I cannot understand that why must be 2,4,8 or 16 transfers? Is there some design issue?

    Hope someone can help,thank you…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Memory controller for AHB, dual (or multi) channel

    David
    David

    Hi, I am looking for a memory controller for AHB, dual (or multi) channel.

    I found one in the ARM site but for AXI.

    Thank you

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
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