• Please help about AMBA AXI 3.0

    Kiêm Nhật Minh
    Kiêm Nhật Minh

    I am a junior ASIC engineer. At the moment, I have three the question about AMBA AXI 3.0

    1. No combination paths between master and slave, all timing path must be registered. Why the VALID and READY signals can assert in the same time ?

    2. In the FIXED…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • AXI4: Write-Alignemnent modes? Partial writing with write strobes possible?

    Martin Trummer
    Martin Trummer

    Hi guys,

    I have two questions related to the write-strobing in AXI4. Both examples work on a 32-bit bus.

    First consider an unaligned access on address 0x1.

    Can this access be created in 2 ways?

    1) Addr=0x0, Wrstrb=1110

    2) Addr=0x1, Wrstrb=0111

    In the second…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • hi. i wonder AMBA 3.0 AXI difference of data interleaving and write data interleaving

    In-Gyu.Lee
    In-Gyu.Lee

    Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

    recently, i read "AMBA® AXI Protocol.pdf". but i have two questions about AXI after reading.



    as you can see the first picture, slave send the read…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • hi. amba 3.0 axi interleaving

    In-Gyu.Lee
    In-Gyu.Lee

    I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

    recently, i read "AMBA® AXI Protocol.pdf". but i have two questions about AXI after reading.


    i wonder about interleaving and out-of order.

    AXI supports…

    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • hi. i wonder AMBA 3.0 AXI out-of order - WID & RID

    In-Gyu.Lee
    In-Gyu.Lee

    Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

    Recently, I read "AMBA AXI Protocol.pdf". but i have two questions about AXI after reading.

    Firstly, i very wonder AWID, WID and BID when write transaction…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • hi. i wonder AMBA 3.0 AXI handshake

    In-Gyu.Lee
    In-Gyu.Lee

    Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

    recently, i read "AMBA® AXI Protocol.pdf". but i have three questions about AXI after reading.

       

    firstly, i very wonder the handshake…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • AXI4: Wider transactions than BUS width allowed?

    Robert Schilling
    Robert Schilling

    Hi AXI-experts,

    Does AX4 support burst sizes larger than the bus width?

    Narrow transactions are allowed, but do wider transactions also work?

    Best regards,

    Robert

    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Questions on AXI4

    Naveen
    Naveen

    I have bunch of questions related to AXI. Can someone help me by answering those?

    AxSize can be varied across multiple transactions?

    whose duty is to set byte strobe in a transfer? Is it the master which should generate byte strobes along with un-aligned…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Reason for having decouple write address, data channels in AXI4

    Naveen
    Naveen

    Can someone explain me the advantage of having decouple write address, data channels in AXI4?

    In AXI3 with data interleaving we can have multiple masters sending data to various clients but in case of AXI4 we don't support interleaving so how decoupled…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Question for AXI responce when access error

    Jun Usami
    Jun Usami

    HI,

    Does anyone know the minimum number of error responce (wready & rvalid) when AxLEN = 15?

    Does it need to respond 16th? or we can respond 1 only?

    Regards,

    -GARO

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Difference between FIXED and INCR burst in AXI?

    jayesh
    jayesh

    For any burst transfer Master has to pass only first address, for the consecutive transfer address calculation is taken care by Slave. So i want to know what is the basic difference in FIXED and INCR burst transfer?

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • About AXI4 address channel and data channel handshake sequence

    田永丰
    田永丰

    I wonder whether the read/write data channel handshake must occur or assert after the address channel handshake completed?

    For example the master device will wait ARREADY assert or ARVALID dessert, before assert the RREADY?

    Remark:

    Just now, I noticed that…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Use of WVALID signal in AXI

    Ronnie Dominic Joseph
    Ronnie Dominic Joseph

    In AXI, does the rising and falling edge of the WVALID signal signify the start and end of a write burst? Can the WVALID signal go low before the write request for all the transfers in that burst are issued?

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Significance of the WVALID signal in AXI

    Ronnie Dominic Joseph
    Ronnie Dominic Joseph

    In AXI, does the rising and falling edge of the WVALID signal signify the start and end of a write burst? Can the WVALID signal go low before the write request for all the transfers in that burst are issued?

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • The Non-Secure Access IDentity (NSAID) of TZC-400

    wangyong
    wangyong

    Hi experts,

    I get the following information about NSAID from TZC-400 trm.
    The Non-Secure Access IDentity (NSAID) input identifies the source interface of a transaction to a filter unit.
    When in Non-secure state the NSAID inputs identify the master that…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • question about burst cross 4KB boundary

    chinatiger
    chinatiger

    AXI Spec指出:Burst can not cross 4KB boundary.

    请问一下:

    如果burst transaction指定的地址越过4KB bounday,会有exception发生吗?

    best wishes,

    • Answered
    • over 6 years ago
    • 中文社区
    • 中文社区论区
  • Can AXI data channel drop a burst?

    Ton
    Ton

    Hello,

           I have a question regarding the AXI protocol, which I can seem to find the answer from the spec.

           On the AXI read bus.

           If the master send the slave 10 read burst commands…

    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • AXI FIXED burst ; Wr/Rd narrow transactions.

    Tsach
    Tsach

    1. I'm examining AXI burst of FIXED type.

    2. Data bus width is of 128bit.

    3. case scenario WRITE:

        awlen    = 2 (3 write transfers)

        awsize  = 2 (32bit per each transfer)

        awburst = 0 (FIXED)…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • AXI WR address channel info arriving before, or, after WR data channel info.

    Tsach
    Tsach

    Hello,

    Regarding AXI WR transaction.

    I'm interested to know what happens if on an AXI write transaction, the WR data channel put the channel info before the address channel info is valid.

    This means that in order to complete the transaction, sometimes…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • MakeUnique Transaction (ACE protocol)

    Rakesh Reddy
    Rakesh Reddy

    Hi.,

    As we know that there is a MakeUnique transaction in ace protocol, can anyone tell me how we can initiate this transaction..? I mean what is the respective signal in AXI4/ACE that allows us to set a master to initiate this MakeUnique transaction.…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Hi, regarding AXI wrte strobe functionality...

    Tsach
    Tsach

    I'm trying to understand the write strobe functionality for a 128bit bus width, burst type FIXED.

    Case scenario:

    AXI bus width 128bit.

    awlen    = 3 (4 write transfers)

    awsize  = 2 (32bit per each transfer)

    awburst = 0 (FIXED)

    awaddr…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Are there any restrictions for the width of an address signal in an AXI4 interface?

    Martin Stolpe
    Martin Stolpe

    Hello,

    in the AXI4 specification I didn't find anything mentioned about width restrictions for the address signal. I'm currently trying to simulate a component which I wrote in VHDL which provides an AXI4 Slave interface. The BFM I'm using to simulate…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • AXI Write data interleaving

    Naveen
    Naveen

    Hello Everyone,

    [This not specific to AXI3/4] Can someone give an example on how write data interleaving works? Is it used only when we have multi-master cases? or its possible with single-master cases also?

    In case if we have 2 burst transfers with A …

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Address handshaking in AXI4

    Rajesh Pandey
    Rajesh Pandey

    Hi  there,

    I have question regarding handshaking in the AXI protocol.Currently i am designing  decorder for AXI4-Lite master .

    While doing the write adress  transaction, AWVALID  depends upon write enable.AWVALID is high when write enable signal…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • In read or write transaction in AXI.what happen if data transaction  is before address.

    Rajesh Pandey
    Rajesh Pandey

    HI there,

    I have question regarding transaction in AXI4 bus (or any other bus). What happens  in write any read action when data transaction (handshaking) occurs before  address  transaction (handshaking) ?

    Will the data be written to the…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
<>