How to use the PADDR of the APB for receiving and sending data through APB?

The design is implemented on a System On Chip (SoC)

The processor is Cortex-M3 32-bit which is interfaced to an FPGA fabric where a processing of some variables will take place. The variables are sent from the processor to the FPGA fabric, and they are…

Hi All,

I have a question about assert timing of PSTRB and PPROT.

I think APB4 spec (IHI0024C_amba_apb_protocol_spec.pdf) does not describe when PSTRB and PPROT should be asserted.
I guess these signals should be asserted while PSEL is high like PADDR…

Hi All,

I have a question about assert timing of PSTRB and PPROT.

I think APB4 spec (IHI0024C_amba_apb_protocol_spec.pdf) does not describe when PSTRB and PPROT should be asserted.
I guess these signals should be asserted while PSEL is high like PADDR…

1)the APB uses massive memory-I/O accesses.what is that massive memory-I/O accesses?

1)what is the difference between with wait state and with no wait state(read/write)?what are the advantages of both in APB?

Hi, 

I was trying to understand the state machine of an APB. I was curious on how the PREADY signal is triggered low so that it can exit from  the ACCESS state? 

If anyone could help me with this basic question, it'll be of great help thank you. :)…

How is it possible for AMBA bus protocol to communicate between ASB bus and APB bus,if they operate in different frequency's? ASB is high performance high frequency bus and APB is low performance low frequency bus..how that communication is happening…

Hello All,

Here at IP Level verification we have no issues as the Master APB does not latch the PREADY, but at SOC Level with multiple APB Slaves 

The Master performs some transaction with APB SLAVE 1 and before switching to APB SLAVE 2 , it disables the…

Hi,

   Can you please help me in writing assertions to take care on multiple transfer in APB bus?

Thanks,

Rakesh

Hello,

in my recent design I have used a processor with Cortex-A5 core (it is SAMA5D27 from Microchip). There is one critical task which needs to be performed in real-time. Could you, please, give me a hint on how to configure the processor for that?

Hi experts Ash Wilding, Mark Nicholson,

I'm trying to configure some peripherals like NIC of the Juno as the secure peripherals.

By checking the material I found that TrustZone Protection Controller(TZPC) can achieve this goal while I do not find any…

PENABLE indicates the second and subsequent cycles of an APB transfer till PREADY goes HIGH.

APB transfer can be considered as complete when PSEL==1 and PREADY==1 ignoring PENABLE==1 and PREADY==1 should be considered only after second and subsequent cycles…

Hi,

 I have tried to find a quick reference for AXI, AHB & APB to no avail, and after having to flit between the various documents and tables, I eventually created my own.

So not sure of the legal ramifications of posting this elsewhere and whether…

Hi All,

      Now i am focusing on the apb 2.0 specification. 

     How to perform a continuous transfer in apb 2.0 . I read some forum , But i did't get a idea.

      If anyone know the continuous transfer in apb 2.0 ,Please share the waveform . It;s easily…

How can I get apb protocol assertions on arm official site? Thanks in advance, KMK

PSTRB signal indicates which byte lanes to update during a write transfer.

it shows that the bus contain valid data, when PSTRB[3:0]=1111.

why we need bus instead of single bit PSTRB signal?