• amba ahb

    vinod474
    vinod474

    hi,

    Is HREADY is used by the slave  to notify the master that it is ready to receive or to indicate transfer is completed??

    thanks in advance

    • over 3 years ago
    • System
    • SoC Design forum
  • DesignStart Pro: APB on FPGA via Quartus Prime

    ag4inst4ll0dds
    ag4inst4ll0dds

    Hello,

    I try to implement the Cortex-M3 processor on an FPGA via Quartus Prime. I set up the SSE050 Subsystem and tried to connect several peripherals to the board. I want to test the functionality with a uVision project lighting some LEDs. To have access…

    • Answered
    • over 2 years ago
    • DesignStart
    • DesignStart forum
  • Regarding WRAP burst calculation in AXI4

    pavan316
    pavan316

    Could you please help me on this topics in AXI4 protocal ::

    1. what is meant by Aligned and Unaligned address?

    2.How can I calculate WRAP boundary calculation in AXI4? please explain with example?

    • Answered
    • over 2 years ago
    • System
    • SoC Design forum
  • AXI WVALID before AWVALID

    srp
    srp

    what happen if WVALID asserted before AWVALID ??

    • Answered
    • over 2 years ago
    • System
    • SoC Design forum
  • In case of AXI4 lite protocol,what is the relation between BValid signal and Wvalid signal?

    Nitin Dixit
    Nitin Dixit

    In case of AXI4 lite protocol,whether BValid should be asserted before WVALID signal deassertion? what is the legal case?

    • over 2 years ago
    • System
    • SoC Design forum
  • AXI4-lite :Wready dependency on Awvalid and Wvalid

    Nitin Dixit
    Nitin Dixit

    In specification it is mentioned that WREADY signal can wait for AWVALID and WVALID signals.

    Does it mean that WREADY signal should be asserted only after assertion of AWVALID and WVALID signals.

    What is the relation between these signals?

    and performance…

    • over 2 years ago
    • System
    • SoC Design forum
  • AHB Lite Response

    Muthuvenkatesh
    Muthuvenkatesh

    Hi All,

                               I have doubt in ahb_lite hresp signaling when the address phase is extending.

    In the following diagram transfer address c is extending because of data phase of B.

    In 3rd clk cycle address C is sampled so that shall we expect the…

    • Answered
    • over 2 years ago
    • System
    • SoC Design forum
  • Relation between Hsel and Hready in AMBA AHB

    Purva
    Purva

    Hi,

    In my design I am having a scenario where my Hsel goes low during the data phase of a transfer and Hready goes high one cycle after that? (i.e hready high during address phase low during data phase and high again in the follwoing cycle 1->0 -> 1)…

    • over 2 years ago
    • System
    • SoC Design forum
  • AHB_LITE Extended address phase

    Muthuvenkatesh
    Muthuvenkatesh

    Hi All ,

                          The following figure shows the INCR4 burst transaction.

    Here the address increment is happening in each clk cycle  As per AHB protocol Single outstanding address is allowed.

    What are the possible adjustment has to be made for this transaction…

    • Answered
    • over 2 years ago
    • System
    • SoC Design forum
  • needs some clarification

    bala devi
    bala devi

    Difference between axi_4 and axi4_alite?

    • Answered
    • over 2 years ago
    • System
    • SoC Design forum
  • Difference btw AXI3 and AXI4

    Muthuvenkatesh
    Muthuvenkatesh

    Hi All ,

                Can anyone please tell the difference btw AXI3 and AXI4.

    Regards

    Muthuvenkatesh

    • Answered
    • over 2 years ago
    • System
    • SoC Design forum
  • Write strobe for AXI4 lite

    sandhya.moorthy
    sandhya.moorthy

    what are the possible values of strobe for a half word transfer in AXI4 lite? 

    Are these following values on WSTRB valid ?

    -1001

    -0101

    -1010

    • over 2 years ago
    • System
    • SoC Design forum
  • needs some clarifiaction

    bala devi
    bala devi

    hi,

    what are the purpose of interconnect..?and why we nedd address routing table..in axi4

    • over 2 years ago
    • System
    • SoC Design forum
  • Please send the APB 3.0 spec

    bala devi
    bala devi

    Can you please send me the AMBA APB 3.0 specification for reference.

    • over 2 years ago
    • System
    • SoC Design forum
  • Error scenario in AHB protocol

    VijeyShankar
    VijeyShankar

    Hi,

     I am developing a RTL code for AHB lite - AXI bridge. I want to understand what are the possible error scenarios in AHB?

    1.I can think of invalid address as the only case. Is there any other scenario?

    2. I am performing a INCR4 transfer on AHB side…

    • Answered
    • over 2 years ago
    • System
    • SoC Design forum
  • needs some clarification

    bala devi
    bala devi

    Hi

    i have one doubt..in apb protocols...what is the difference between wait_state and no_wait_state in apb protocopls?

    • Answered
    • over 2 years ago
    • System
    • SoC Design forum
  • Narrow burst (32 bit read) on a 64 bit data bus AXI read transaction

    VijeyShankar
    VijeyShankar

    Hello All,

      I have a 64 bit data bus and I am making a 32 bit INCR with length 4(INCR4) write on it by giving the starting address.

    When  I read back at the same address, I am getting as 2 64 bit data each for 2 clock cycles. Why is this?

    Scenario : Single…

    • over 2 years ago
    • System
    • SoC Design forum
  • Sampling on positive edge of clock of slave in AXI3

    karukaka
    karukaka

    How do you confirm if a slave is sampling on positive edge of clock only ? How can we prove this in simulation

    • over 2 years ago
    • System
    • SoC Design forum
  • Is there relation between the de-assertion of BVALID and BREADY signals ?

    Amit Mishra
    Amit Mishra

    Hi,

    I am aware that like other channels, the handshaking signals of the Write Response can assert in any order (that means BVALID and BREADY can assert either together at the same clock edge of one after the other in both the orders). But is there any…

    • over 2 years ago
    • System
    • SoC Design forum
  • Looking for pin/bit accurate AXI4 SystemC models

    Vijayvithal
    Vijayvithal

    Hi,

    I am creating a systemC model for a peripheral which has an AXI4 interface.

    Is there a bit and pin accurate AXI4 SystemC model similar to the ones available for OCP?

    Is it available from ARM, a ThirdParty vendor, or the opensource community?

    • over 2 years ago
    • System
    • SoC Design forum
  • Alignment Address Calculation in AHB

    Aman007kc
    Aman007kc

    Hello I want to know the calculation for

    HSIZE=2 and Wrap 8

    and starting address is 0x4

    and how we are doing alignment ???

    • over 1 year ago
    • System
    • SoC Design forum
  • AXI4 Burst Transactions

    surajrgupta
    surajrgupta

    I am new to AXI4 protocol. I would like to know how many clock cycles are required to complete a AXI4 burst write transaction.

    Eg. Burst length- Two , Burst size 16 bytes.

    Please give me answers for different types of data bus width say for bus width …

    • Answered
    • over 1 year ago
    • System
    • SoC Design forum
  • What is AMBA 5 CHI and how does it help?

    Bruce Mathewson
    Bruce Mathewson

    At last the time has finally come when I can talk about AMBA 5 - the next generation of ARM interface standard.

    So, what's new?

    To start this discussion it is worth answering a question I frequently get asked, which often goes along the lines of…

    • over 7 years ago
    • Processors
    • Processors blog
  • Whitepaper - ARMv8-M Architecture Technical Overview

    Joseph Yiu
    Joseph Yiu

    The next generation of ARM Cortex-M processors will be powered by a new architecture version called ARMv8-M architecture. This document provides a technical overview of various enhancements in the new architecture, as well as an introduction to the security…

    • Whitepaper - ARMv8-M Architecture Technical Overview.pdf
    • over 4 years ago
    • Processors
    • Processors blog
  • Partnerships and the Myths of System Resilience

    Andrew Hopkins
    Andrew Hopkins

    At the 55th Design Automation Conference 2018

    The Design Automation Conference (DAC) brings together an interesting mixture of EDA and IP companies enabling tool users, licensees and partners to meet. Automotive and functional safety continued to be major…

    • over 2 years ago
    • System
    • Embedded blog
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