hi,
Is HREADY is used by the slave to notify the master that it is ready to receive or to indicate transfer is completed??
thanks in advance
hi,
Is HREADY is used by the slave to notify the master that it is ready to receive or to indicate transfer is completed??
thanks in advance
Hello,
I try to implement the Cortex-M3 processor on an FPGA via Quartus Prime. I set up the SSE050 Subsystem and tried to connect several peripherals to the board. I want to test the functionality with a uVision project lighting some LEDs. To have access…
Could you please help me on this topics in AXI4 protocal ::
1. what is meant by Aligned and Unaligned address?
2.How can I calculate WRAP boundary calculation in AXI4? please explain with example?
In case of AXI4 lite protocol,whether BValid should be asserted before WVALID signal deassertion? what is the legal case?
In specification it is mentioned that WREADY signal can wait for AWVALID and WVALID signals.
Does it mean that WREADY signal should be asserted only after assertion of AWVALID and WVALID signals.
What is the relation between these signals?
and performance…
Hi All,
I have doubt in ahb_lite hresp signaling when the address phase is extending.
In the following diagram transfer address c is extending because of data phase of B.
In 3rd clk cycle address C is sampled so that shall we expect the…
Hi,
In my design I am having a scenario where my Hsel goes low during the data phase of a transfer and Hready goes high one cycle after that? (i.e hready high during address phase low during data phase and high again in the follwoing cycle 1->0 -> 1)…
Hi All ,
The following figure shows the INCR4 burst transaction.
Here the address increment is happening in each clk cycle As per AHB protocol Single outstanding address is allowed.
What are the possible adjustment has to be made for this transaction…
Hi All ,
Can anyone please tell the difference btw AXI3 and AXI4.
Regards
Muthuvenkatesh
what are the possible values of strobe for a half word transfer in AXI4 lite?
Are these following values on WSTRB valid ?
-1001
-0101
-1010
hi,
what are the purpose of interconnect..?and why we nedd address routing table..in axi4
Can you please send me the AMBA APB 3.0 specification for reference.
Hi,
I am developing a RTL code for AHB lite - AXI bridge. I want to understand what are the possible error scenarios in AHB?
1.I can think of invalid address as the only case. Is there any other scenario?
2. I am performing a INCR4 transfer on AHB side…
Hi
i have one doubt..in apb protocols...what is the difference between wait_state and no_wait_state in apb protocopls?
Hello All,
I have a 64 bit data bus and I am making a 32 bit INCR with length 4(INCR4) write on it by giving the starting address.
When I read back at the same address, I am getting as 2 64 bit data each for 2 clock cycles. Why is this?
Scenario : Single…
How do you confirm if a slave is sampling on positive edge of clock only ? How can we prove this in simulation
Hi,
I am aware that like other channels, the handshaking signals of the Write Response can assert in any order (that means BVALID and BREADY can assert either together at the same clock edge of one after the other in both the orders). But is there any…
Hi,
I am creating a systemC model for a peripheral which has an AXI4 interface.
Is there a bit and pin accurate AXI4 SystemC model similar to the ones available for OCP?
Is it available from ARM, a ThirdParty vendor, or the opensource community?
Hello I want to know the calculation for
HSIZE=2 and Wrap 8
and starting address is 0x4
and how we are doing alignment ???
I am new to AXI4 protocol. I would like to know how many clock cycles are required to complete a AXI4 burst write transaction.
Eg. Burst length- Two , Burst size 16 bytes.
Please give me answers for different types of data bus width say for bus width …
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To start this discussion it is worth answering a question I frequently get asked, which often goes along the lines of…
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