Hi,

In AMBA AHB:-

     For two clock cycle SPLIT or RETRY response, hgrant must be low after 1st clock cycle of SPLIT or RETRY response.

   q)  For two clock cycle ERROR response, is it mandatory of hgrant must be low after 1st clock…

What would happen if HREADY will be lower not after address phase, but according to HW internal logic that wants to hold CPU for some clock cycles.

Thanks

I am a Digital Verification Design Engineer.

Currently, I am in the process of developing an UVM Test Bench for AHB 2.0.

I have following questions.

1) From AHB Master side, Can BUSY cycles be inserted in middle of INCR16 burst?

2) From AHB Master side,…

Why the address boundary for AHB burst should not cross 1KB??

And in case of burst operation, is that every beat the address increment taken care by master?

Hi,

I trying to build the peripheral around Cortex-M0 IP core thorugh AHB-lite system. Right now I have to integrate Cortex-M0 with the DDR2 SRAM (1Gb) through AHB lite.

I searched on  internet which shows interfacing only through core generator (MIG…

I have a shared memory in DDR  --- shared between two separate ARM execution environments (say A and B)  in a heterogeneous compute SoC.

SW on each execution units (A and B) Reads and Writes to this shared location (imagine a array/matrix that…

I see in the documentation site that ARM offers up some bus functional models to simulate both a 32 and a 64 bit AHB bus master in Verilog RTL.

Where do I find these models, and what is the cost?

I am working to verify a customer's AHB peripheral, and…

Hi,

   I have a question on AMBA AHB, Let us assume we are firing INCR4 burst from master M1.

  Let us assume  EBT is happened during 2nd transfer address phase of INCR4 burst (i.e Master M1 lost its grant without driving of its data phase and…

if i want to read 16-bytes from 'hxx00 address(32-byte aligned address) on a 32-byte width data bus, what should be the arsize[3:0]? i donot want to put arsize='h5 as it would result in a performance penality if the slave is DDR controller.

Hi All,

This question is regarding "ReadNoSnoop" transaction of AMBA- ACE protocol.

If "ReadNoSnoop" transaction is used in a region of memory that is not shareable with other masters, then how can the cache line have have "Shared Clean" or "Shared…

In the PL310 TRM, the definition of the CACHE_ID register define the RTL release as the lower bits of the register.

To translate this RTL to a revision information, it is stated that

"RTL release 0x9 denotes r3p3 code of the cache controller. See the Release…

Hi AXI-experts,

Does AX4 support burst sizes larger than the bus width?

Narrow transactions are allowed, but do wider transactions also work?

Best regards,

Robert