• Simplifying workload modeling with AMBA ATP Engine

    Francisco Socal
    Francisco Socal

    We are pleased to announce the release of the AMBA ATP Engine, an open-source implementation of AMBA ATP (Adaptive Traffic Profiles). The Engine significantly simplifies the adoption of AMBA ATP for workload modeling and accelerates the research and development…

    • 1 month ago
    • System
    • SoC Design blog
  • Getting started with AMBA and AMBA AXI

    NickT
    NickT

    As you may be aware, far from being a misspelled fossilized tree resin, AMBA is a freely available open standard for the connection and management of functional blocks in a system-on-chip (SoC). Since the mid-90s, AMBA has been implemented by vendors…

    • 3 months ago
    • Processors
    • Processors blog
  • New Arm online training course: Introduction to the AMBA ACE protocol

    NickT
    NickT

    Arm is pleased to announce a new online training topic - An introduction to the AMBA ACE protocol.

    About the course

    This training topic covers essential information on Arm’s AMBA ACE protocol. Hardware system-level coherency enables the sharing of…

    • 10 months ago
    • Processors
    • Processors blog
  • Please explain some of the new ACE5 signals in relation to the MASTER and INTERCONNECT behavior

    armchronos
    armchronos

    Hi,

    The AMBA5 spec for ACE5 shows some new signals versus ACE4 :

    VAWQOSACCEPT

    VARQOSACCEPT

    AWAKEUP

    ACWAKEUP

    SYSCOREQ

    SYSCOACK

    How are these used in an SOC system ?

    For example, I think but I'm not usre if VAWQOSACCEPT, VARQOSACCEPT is output by each slave…

    • Answered
    • over 2 years ago
    • System
    • SoC Design forum
  • How do AMBA, CCIX and Gen-Z address the needs of the data center?

    Jeff Defilippi
    Jeff Defilippi

    Interconnects and open standards have been a hot topic lately. A couple of weeks ago, Arm announced the CoreLink CMN-600 Coherent Mesh Network and CoreLink DMC-620 Dynamic Memory Controller IP, which support AMBA 5 CHI, the open standard for high performance…

    • over 3 years ago
    • Processors
    • Processors blog
  • Partnerships and the Myths of System Resilience

    Andrew Hopkins
    Andrew Hopkins

    At the 55th Design Automation Conference 2018

    The Design Automation Conference (DAC) brings together an interesting mixture of EDA and IP companies enabling tool users, licensees and partners to meet. Automotive and functional safety continued to be major…

    • over 1 year ago
    • System
    • Embedded blog
  • Memory System is Key to User Experience with Cortex-A73 and Mali-G71

    Neil Parris
    Neil Parris

    By now you would have read the news about the latest ARM® Cortex®-A73 processor and Mali™-G71 GPU. These new processors allow for more performance in an ever thinner mobile device, and accelerate new use cases such as Virtual Reality …

    • over 4 years ago
    • Processors
    • Processors blog
  • 扩展系统一致性 - 第 3 部分 - 性能提升和 CoreLink CCI-500 简介

    Song Bin 宋斌
    Song Bin 宋斌

    原文地址:Extended System Coherency - Part 3 – Increasing Performance and Introducing CoreLink CCI-500

    原作者:neilparris

    在本周,我们宣布推出旨在增强高端移动体验的全新 IP 套件。 此套件的核心是 ARM CoreLink CCI-500 缓存一致性互联,它以率先获得市场成功的上一代互联为基础,拓展了 ARM 系统在性能和更低功耗上的领先地位。

    一年前我发表了与本主题相关的第一篇博文,…

    • over 5 years ago
    • 中文社区
    • 中文社区博客
  • 扩展系统一致性 - 第 1 部分 - 缓存一致性基本信息

    Song Bin 宋斌
    Song Bin 宋斌

    原文地址:Extended System Coherency - Part 1 - Cache Coherency Fundamentals

    原作者:neilparris

    简介

    TechCon 2013 的主题是“智能互联”,而在许多方面,硬件系统一致性是 SoC 中智能互联的一个重要部分。我在今年的演讲“移动等平台的扩展系统一致性”中介绍了缓存一致性的基本信息,探讨了相关实施,也研究了一些用例。 本文是系列博文中的第一篇,首先介绍缓存一致性的基本信息。

    …
    • over 5 years ago
    • 中文社区
    • 中文社区博客
  • Extended System Coherency: Part 1 - Cache Coherency Fundamentals

    Neil Parris
    Neil Parris

    Chinese Version 中文版:扩展系统一致性 - 第 1 部分 - 缓存一致性基本信息

    Introduction

    The theme of TechCon 2013 was “Where intelligence connects” and in many ways hardware system coherency is an important part of connecting the intelligence of an SoC. This year I presented…

    • over 6 years ago
    • Processors
    • Processors blog
  • How to Measure and Optimize the System Performance of a Smartphone RTL Design - Part 4

    Nick
    Nick

    By William Orme, Strategic Marketing Manager, Arm and Nick Heaton, Distinguished Engineer, Cadence

    This is Part 3 of a 4 part series. Links below

    Part 4

    Cadence Interconnect Workbench

    We have seen how a systematic process can be applied to validating…

    • over 6 years ago
    • System
    • SoC Design blog
  • How to Measure and Optimize the System Performance of a Smartphone RTL Design - Part 3

    Nick
    Nick

    By William Orme, Strategic Marketing Manager, Arm and Nick Heaton, Distinguished Engineer, Cadence

    This is Part 3 of a 4 part series. Links below

    Part 3

    Use-case Performance Analysis

    In the previous two parts we introduced the challenges facing designers…

    • over 6 years ago
    • System
    • SoC Design blog
  • How to Measure and Optimize the System Performance of a Smartphone RTL Design - Part 2

    Nick
    Nick

    By William Orme, Strategic Marketing Manager, Arm and Nick Heaton, Distinguished Engineer, Cadence

    This is Part 2 of a 4 part series. Links below

    Part 2

    Performance Characterization

    Because of the complexity of assembling and configuring the multitude…

    • over 6 years ago
    • System
    • SoC Design blog