Hi,

in the AMBA/AXI Protocol specification, I read

There must be no combinatorial paths between input and output signals on both master and slave interfaces.

What signals, explicitly, may not have combinatorials between them?

Thanks in advance.

Hi,

I am reading ACE protocol and i am confused about when to use cache maintenance transactions. On what basis should i decide when to use cache maintenance transaction and which transaction to be used?

Can anyone please help?

Hi,

We are using Cortex-R5F. Through the AXI slave interface, we are accessing the data cache data RAM, tag RAM and dirty RAM. We would like to know how we can associate the bits found in the data RAM with the bits found in the tag RAM. For example,…

Hi,

In AXI4/5 spec (IHI0022F), it listed a set of signal dependencies for read and write transactions.

My problem is in Figure A3-7 AXI4 and AXI5 write transaction handshake dependencies. It noted that "Dependencies on the assertion of WVALID also require…

Hi,

In the AXI spec it is mentioned that , even in case of ERROR response, the slave needs to respond with the exact number of beats and indicate the response with each beat.

Now my question here is if the response is going to be ERROR(lets say SLVERR…

Hi,

In AXI4, spec changed the definition of the definition of AxCACHE[3:2] from Write Allocate/Read Allocate to be Allocate/Other Allocate.

But is there any concrete reason for this change? Actually I found some related statements from spec, but I couldn…

Hello,

We are using ARM Matrix IP that is acting as a Master and using our VIP as a slave.

ARM Matrix is sending a initiating a WRITE Transfer on a slave when HREADY is low, but not keeping control signals stable till HREADY becomes high.

So the questions…

Hi,

I want to know which transaction should be issued by ACE interface on the channel when a flush/clean request is being processed by the cache?

Can anyone please help.

Regards,

Taniya Garg

In Section C1.3 Channel Overview of the AMBA_AXI_and_ACE protocol specifications, It is mentioned under "Store operations where the cache line is already cached" as :

The initiating master component requests a unique copy of the cache line…

Hi ,

   What is the purpose of removing ID's (WID) in AXI4 ?

If it because of reduction of pin count then We lost the " Write Data Interleaving" and "Out Of Order " Transaction features. Can you please tell me if any other reasons...(Arm Spec says.…

Hi,

I was reading the CHI architecture specification but there is no mention of electrical characteristics such as

the clock frequency for the CHI interface.

What is the max and min frequency for CHI interface ?

Thanks,

David

What is byte lane in AXI?

In read transfres how the slave indicates the transaction is over?

If the slave is not able to process read request from master, which response is expected from slave?

Why burst must not cross 4kb  in AXI ?

Hii,

Greetings !!

I would like to know the standard operating clock frequency and data rate of AMBA- apb, ahb, axi.

Please someone help me out.

Thanks in advance

Regards

Ujjwal

what is the difference between overlapping and out of order transfers in Aciform the explanation it seems that both are same is this the case?

Why the word boundary in AXI is 4k?

Consider Data interface is 64 bit.
It is Write transfer.
AXI master need to transfer 11 bytes and starting address is 0. Anyone suggest which one is a valid among below mentioned two scenarios.

Scenario 1:
Burst -> Address:0, size:3, length:1, burst_type…