• How to map tag RAM banks to data cache lines in Cortex-R5?

    Etienne Alepins
    Etienne Alepins

    Hi,

    We are using Cortex-R5F. Through the AXI slave interface, we are accessing the data cache data RAM, tag RAM and dirty RAM. We would like to know how we can associate the bits found in the data RAM with the bits found in the tag RAM. For example,…

    • over 1 year ago
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