• How does128Byte WriteLineUnique transaction map to a cache with 64Byte cache line size?

    Hanan
    Hanan

    Hello,

    I have an IP with an ACE-Lite I/F which can issue a 128Byte write transaction with a "WriteLineUnique" type. I  the system there will be a cortex A7 master(64bytes cache line). My question is: in case of such transaction (WriteLineUnique with 128bytes…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • AMBA 4 ACE and Hardware Cache Coherency - Top 5 Questions

    Neil Parris
    Neil Parris

    I thought I'd post a short blog post about commonly asked questions on AMBA 4 ACE and system coherency.

    What does ACE mean?

    ACE is the "AXI Coherency Extensions" introduced with the AMBA 4 specification released in 2011. For those of you thinking "What…

    • over 6 years ago
    • Processors
    • Processors blog
  • big.LITTLE and AMBA 4 ACE keep your cache warm and avoid flushes

    Neil Parris
    Neil Parris

    Updated 29th October 2013


    High performance and power efficiency are critical to the latest mobile devices, and AMBA® 4 ACE™ is a fundamental technology supporting ARM's big.LITTLE processing. In case you missed the announcements, the big…

    • over 6 years ago
    • Processors
    • Processors blog