• How to use the amba bus?

    Idan
    Idan

    Hello,

    i have the Zedboard which contains arm Cortex-A9 cortex with the amba bus..

    i have searched a lot but I probaly miss the point.

    i want to use data and to transfer  data from the processing system to the programable logic section via the amba bus…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How does128Byte WriteLineUnique transaction map to a cache with 64Byte cache line size?

    Hanan
    Hanan

    Hello,

    I have an IP with an ACE-Lite I/F which can issue a 128Byte write transaction with a "WriteLineUnique" type. I  the system there will be a cortex A7 master(64bytes cache line). My question is: in case of such transaction (WriteLineUnique with 128bytes…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • General Feature of Cortex processors on cache coherency

    techguyz
    techguyz

    Hi Experts,

    Is there any general feature available in the cortex processors to realize the cache lines by DMA through AXI ?

    I found some features like CCI module available to provide this feature in multi-core environment. Other than that, is it possible…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • does ARM v8 bus architecture & related IPs be compatible with v7 core?

    chengliang
    chengliang

    I would like to get some confirmation that if we replace A53/A72 with A7/A9 while the SoC architecture is still based on ARM v8 bus & IPs (e.g. CCI400, NIC400, TZC400, GIC500, BP141), does such design feasible and workable?

    • over 3 years ago
    • System
    • SoC Design forum
  • New AMBA Specification Extends Security to Embedded Design: AMBA 5 AHB5

    Eoin McCann
    Eoin McCann

    The amount of data we generate is growing exponentially. Gartner has predicted that in 2015 the global mobile data traffic will be a total of 52 billion terabytes, an increase of 59 percent on 2014. It’s a staggering number that is driven not just by…

    • over 4 years ago
    • Processors
    • Processors blog
  • 扩展系统一致性 - 第 2 部分 - 实施、big.LITTLE、GPU 计算和企业级应用

    Song Bin 宋斌
    Song Bin 宋斌

    原文地址: Extended System Coherency - Part 2 - Implementation, big.LITTLE, GPU Compute and Enterprise

    原作者:neilparris

    本文是关于硬件一致性系列博文中的第二篇。 在第一篇博文中,我介绍了缓存一致性的基本信息: 扩展系统一致性 - 第 1 部分 - 缓存一致性基本信息

    此部分探讨硬件缓存一致性的实施和用例。

    另有一个详述 CoreLink CCI-500 的第 3 部分: 扩展系统一致性 - 第 3

    …
    • over 5 years ago
    • 中文社区
    • 中文社区博客
  • 扩展 CoreLink 缓存一致性网络系列

    Song Bin 宋斌
    Song Bin 宋斌

    原文地址:Extending the CoreLink Cache Coherent Network Family

    原作者:jdefilippi

    ARM 在过去一个月来忙于专注基础架构领域。在最近举办的 ARM TechCon 2014 大会上,ARM 硅片、OEM 和生态系统合作伙伴展示了他们的新款系统级芯片 (SoC)、硬件和软件平台。此次展会还进行了数场对话,讨论了基础架构目前面临的挑战以及创新需求。Neil Parris 在其最近发布的博文 Heterogeneous Compute Requirements…

    • over 5 years ago
    • 中文社区
    • 中文社区博客
  • Extending the CoreLink Cache Coherent Network Family

    Jeff Defilippi
    Jeff Defilippi

    Chinese Version 中文版:扩展 CoreLink 缓存一致性网络系列

    It has been a busy month for ARM in the infrastructure space. ARM TechCon 2014 started it off with ARM silicon, OEM and ecosystem partners demonstrating their new SoCs, hardware and software platforms. The show…

    • over 5 years ago
    • Processors
    • Processors blog
  • AMBA 4 ACE and Hardware Cache Coherency - Top 5 Questions

    Neil Parris
    Neil Parris

    I thought I'd post a short blog post about commonly asked questions on AMBA 4 ACE and system coherency.

    What does ACE mean?

    ACE is the "AXI Coherency Extensions" introduced with the AMBA 4 specification released in 2011. For those of you thinking "What…

    • over 6 years ago
    • Processors
    • Processors blog