• Cache type and cache operation sequence

    sd
    sd

    I have a shared memory in DDR  --- shared between two separate ARM execution environments (say A and B)  in a heterogeneous compute SoC.

    SW on each execution units (A and B) Reads and Writes to this shared location (imagine a array/matrix that…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum

  • pl310 CACHE_ID register

    Vincent Siles
    Vincent Siles

    In the PL310 TRM, the definition of the CACHE_ID register define the RTL release as the lower bits of the register.

    To translate this RTL to a revision information, it is stated that

    "RTL release 0x9 denotes r3p3 code of the cache controller. See the Release…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum

  • AMBA AXI can set data transfer cacheable or bufferable, I want ask this cache or buffer refer to the cache or buffer inside AXI interconnect or system cache?

    Kun.Niu
    Kun.Niu

    AMBA AXI can set data transfer cacheable or bufferable, I want ask this cache or buffer refer to the cache or buffer inside AXI interconnect or system cache?

    As usual, we talk about cache is mainly refer to the cache inside CPU, but AXI's cache or buffer…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum

  • ACE protocol : Eviction and snoop request at same time

    Chakri Myneni
    Chakri Myneni

    How to handle below scenario ?

    • At time t1 let us suppose L1 data cache is evicting a line and write address is sent on write address channel by asserting AWVALID (AWREADY is high)
    • At same time t1, there is a snoop request from interconnect on snoop address…
    • Answered
    • over 1 year ago
    • System
    • SoC Design forum

  • AMBA AXI CACHE

    srp
    srp

    i am not able to understand working of this CACHE signal pleas explain with simple example.

    thank you!

    • over 2 years ago
    • System
    • Embedded forum

  • Cache Maintenance Transactions

    Taniya Garg
    Taniya Garg

    Hi,

    I am reading ACE protocol and i am confused about when to use cache maintenance transactions. On what basis should i decide when to use cache maintenance transaction and which transaction to be used?

    Can anyone please help?

    • over 1 year ago
    • System
    • Embedded forum

  • How to handle Cache flush in ACE?

    Taniya Garg
    Taniya Garg

    Hi,

    I want to know which transaction should be issued by ACE interface on the channel when a flush/clean request is being processed by the cache?

    Can anyone please help.

    Regards,

    Taniya Garg

    • over 1 year ago
    • System
    • Embedded forum

  • Introducing AMBA 5 CHI protocol enhancements: Specification now available

    Jeff Defilippi
    Jeff Defilippi

    In 2013 Arm announced the AMBA 5 CHI protocol to provide the performance and scale required for infrastructure applications such as networking and data center. The protocol has been highly successful and has been the foundation for Arm many core systems…

    • over 3 years ago
    • System
    • SoC Design blog