• Getting started with AMBA and AMBA AXI

    NickT
    NickT

    As you may be aware, far from being a misspelled fossilized tree resin, AMBA is a freely available open standard for the connection and management of functional blocks in a system-on-chip (SoC). Since the mid-90s, AMBA has been implemented by vendors…

    • 3 months ago
    • Processors
    • Processors blog

  • Readunique and cleanunique transactions in ACE protocol

    het
    het

    In case of readunique transaction cache line is copied into the initiating master's cache(whether it is clean or dirty) and invalidated in snooped master's cache and then store operaation is performed in initiating master's cache line.

    In…

    • 5 months ago
    • System
    • Embedded forum

  • 4-kbyte boundary space

    quy truong
    quy truong
    Note: This was originally posted on 22nd August 2012 at http://forums.arm.com

    Hi there,
    when I read AMBA AXI4 specification, the spec shows that "Bursts must not cross 4KB boundaries to prevent them from crossing boundaries between slaves and to limit the…
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum

  • AXI4: Wider transactions than BUS width allowed?

    Robert Schilling
    Robert Schilling

    Hi AXI-experts,

    Does AX4 support burst sizes larger than the bus width?

    Narrow transactions are allowed, but do wider transactions also work?

    Best regards,

    Robert

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum

  • ACE-Lite Master and Slaves

    Uma
    Uma

    Hello Ashley,

          I have couple of basic doubts w.r.t ACE-Lite Slave.

          The AMBA spec for ACE-Lite says that " ACE-Lite is used by master components that do not have hardware coherent caches". But they can issue transactions…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum

  • Problems with  AXI4  write data channel

    uestc
    uestc

    Hello:

        Suppose there are 2 masters(master0 and master1) and 2 slaves(slave0 and slave1) for AXI4. As AXI4 protocol has removed WID signal for write data channel，When slave0 has received wvaild which is pulled up afte  slave0 has…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum

  • Axi4 Write Transaction

    SelvamThangam
    SelvamThangam

    I got a doubt,Does Master should wait for Bresp to send next Write transaction or it can continuously send the transaction independent for Bresp.

    • over 1 year ago
    • System
    • SoC Design forum

  • AXI-4 questions

    SBR_123
    SBR_123

    Hello,

    I am pretty new to AMBA protocol and I am specifically interested in AXI-4. I have a few fundamental questions related to AXI-4 and I would appreciate if anyone can answer these.

    1) I would like to know how read and write address requests issued…

    • Answered
    • over 4 years ago
    • System
    • Embedded forum

  • Problems about signal dependencies in AXI spec

    Yu-Hsin
    Yu-Hsin

    Hi,

    In AXI4/5 spec (IHI0022F), it listed a set of signal dependencies for read and write transactions.

    My problem is in Figure A3-7 AXI4 and AXI5 write transaction handshake dependencies. It noted that "Dependencies on the assertion of WVALID also require…

    • over 1 year ago
    • System
    • Embedded forum

  • Why AXI4 changed the definition of AxCACHE?

    Yu-Hsin
    Yu-Hsin

    Hi,

    In AXI4, spec changed the definition of the definition of AxCACHE[3:2] from Write Allocate/Read Allocate to be Allocate/Other Allocate.

    But is there any concrete reason for this change? Actually I found some related statements from spec, but I couldn…

    • over 1 year ago
    • System
    • Embedded forum

  • Removal of WID's in AMBA AXI4

    mvenkatesh
    mvenkatesh

    Hi ,

       What is the purpose of removing ID's (WID) in AXI4 ?

    If it because of reduction of pin count then We lost the " Write Data Interleaving" and "Out Of Order " Transaction features. Can you please tell me if any other reasons...(Arm Spec says.…

    • over 1 year ago
    • System
    • Embedded forum

  • How does QoS with priority and ordering allowed with AXI ID?

    tarun4682
    tarun4682

    I have one question for QoS with AXI4:

    Can one master have multiple QoS values?

    Meaning one master issues requests with different QoS values but all with same AXI ID and the interconnect network arbitrates between these requests based on QoS value and…

    • over 3 years ago
    • System
    • SoC Design forum

  • ARM AXI4 protocol assertions trigger errm_wdata_num_prop5 and errm_wlast_stable quesitons

    armchronos
    armchronos

    Hi,

    I'm getting two AXI4 protocol assertion errors.

    For axi4_errm_wlast_stable, I can see why it's flagging an error but functionally it shouldn't be a problem.

    The WREADY =1 for one more cycle when though WVALID=0 and WLAST=0. 

    Is this a…

    • Answered
    • over 2 years ago
    • System
    • SoC Design forum

  • AXI modifiable read access

    arc
    arc

    The AXI protocol description states for modifiable transactions (ARCACHE[1] is asserted):

    "a read transaction can fetch more data than required"

    To me, this can be interpreted in two ways:

    1. The RVALID signal of the slave can be asserted for…
    • Answered
    • over 2 years ago
    • System
    • SoC Design forum

  • unaligned address in AXI protocol

    dorababu
    dorababu

    i am sending data "NEWDATAA"  which is 8 bytes. and  starting address is 5, which is unaligned address then whether my data is loss or not . please explain how the whole transfer will happens. how the strobe will works. is my data start with aligned…

    • over 2 years ago
    • System
    • SoC Design forum

  • AXI4

    Vasu
    Vasu

    In the spec it is mentioned that AXI4 supports high-bandwidth, high-frequency and low-latency operation. How to justify this?  What is the meaning of bandwidth in this context? What are the  values of bandwidth and frequency? How they decide the operating…

    • Answered
    • over 2 years ago
    • System
    • SoC Design forum

  • Regarding WRAP burst calculation in AXI4

    pavan316
    pavan316

    Could you please help me on this topics in AXI4 protocal ::

    1. what is meant by Aligned and Unaligned address?

    2.How can I calculate WRAP boundary calculation in AXI4? please explain with example?

    • Answered
    • over 2 years ago
    • System
    • SoC Design forum

  • needs some clarification

    bala devi
    bala devi

    Difference between axi_4 and axi4_alite?

    • Answered
    • over 2 years ago
    • System
    • SoC Design forum

  • Difference btw AXI3 and AXI4

    Muthuvenkatesh
    Muthuvenkatesh

    Hi All ,

                Can anyone please tell the difference btw AXI3 and AXI4.

    Regards

    Muthuvenkatesh

    • Answered
    • over 2 years ago
    • System
    • SoC Design forum

  • needs some clarifiaction

    bala devi
    bala devi

    hi,

    what are the purpose of interconnect..?and why we nedd address routing table..in axi4

    • over 2 years ago
    • System
    • SoC Design forum

  • AXI4 Burst Transactions

    surajrgupta
    surajrgupta

    I am new to AXI4 protocol. I would like to know how many clock cycles are required to complete a AXI4 burst write transaction.

    Eg. Burst length- Two , Burst size 16 bytes.

    Please give me answers for different types of data bus width say for bus width …

    • Answered
    • over 1 year ago
    • System
    • SoC Design forum

  • AXI4:what will happen if there is a AXI rd and wr concurrently for a same address for a particular slave??

    sourav
    sourav

    AXI4:what will happen if there is a AXI rd and wr concurrently for a same address for a particular slave??

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum

  • AXI4: Unaligned read transactions

    Martin Trummer
    Martin Trummer

    Hi guys,

    I'm new to the AXI ecosystem.

    However, I have one question related to unaligned read transfers.


    Does AXI4 support unaligned read transfers although er are no strobe lines?

    If so, which data on the bus is written?

    To make it easier, discuss it…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum

  • Reason for having decouple write address, data channels in AXI4

    Naveen
    Naveen

    Can someone explain me the advantage of having decouple write address, data channels in AXI4?

    In AXI3 with data interleaving we can have multiple masters sending data to various clients but in case of AXI4 we don't support interleaving so how decoupled…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum

  • About AXI4 address channel and data channel handshake sequence

    田永丰
    田永丰

    I wonder whether the read/write data channel handshake must occur or assert after the address channel handshake completed?

    For example the master device will wait ARREADY assert or ARVALID dessert, before assert the RREADY?

    Remark:

    Just now, I noticed that…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
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