• AMBA3 AXI Relationship Between Channels

    Cao Phi Ho
    Cao Phi Ho

    In the document AMBA3 AXI (3.2 Relationships between the channels)

         Two relationships that must be maintained are:

              • read data must always follow the address to which the data relates…

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    • over 5 years ago
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  • PLEASE HELP ME (AMBA3 AXI)

    Cao Phi Ho
    Cao Phi Ho

    1/ WHY "the width of the ID field at a slave interface is wider than the ID field at a master

    interface"??? Can you please explain in more detail the reason???

    2/ Do AXI protocol have support "read interleaving"???

    Thanks you so much…

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    • over 5 years ago
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  • Please help about AMBA AXI 3.0

    Kiêm Nhật Minh
    Kiêm Nhật Minh

    I am a junior ASIC engineer. At the moment, I have three the question about AMBA AXI 3.0

    1. No combination paths between master and slave, all timing path must be registered. Why the VALID and READY signals can assert in the same time ?

    2. In the FIXED…

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    • over 5 years ago
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  • hi. i wonder AMBA 3.0 AXI difference of data interleaving and write data interleaving

    In-Gyu.Lee
    In-Gyu.Lee

    Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

    recently, i read "AMBA® AXI Protocol.pdf". but i have two questions about AXI after reading.



    as you can see the first picture, slave send the read…

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    • over 5 years ago
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  • hi. amba 3.0 axi interleaving

    In-Gyu.Lee
    In-Gyu.Lee

    I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

    recently, i read "AMBA® AXI Protocol.pdf". but i have two questions about AXI after reading.


    i wonder about interleaving and out-of order.

    AXI supports…

    • over 5 years ago
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  • hi. i wonder AMBA 3.0 AXI out-of order - WID & RID

    In-Gyu.Lee
    In-Gyu.Lee

    Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

    Recently, I read "AMBA AXI Protocol.pdf". but i have two questions about AXI after reading.

    Firstly, i very wonder AWID, WID and BID when write transaction…

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    • over 5 years ago
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  • hi. i wonder AMBA 3.0 AXI handshake

    In-Gyu.Lee
    In-Gyu.Lee

    Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

    recently, i read "AMBA® AXI Protocol.pdf". but i have three questions about AXI after reading.

       

    firstly, i very wonder the handshake…

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    • over 5 years ago
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  • Reason for having decouple write address, data channels in AXI4

    Naveen
    Naveen

    Can someone explain me the advantage of having decouple write address, data channels in AXI4?

    In AXI3 with data interleaving we can have multiple masters sending data to various clients but in case of AXI4 we don't support interleaving so how decoupled…

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    • over 5 years ago
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  • Question for AXI responce when access error

    Jun Usami
    Jun Usami

    HI,

    Does anyone know the minimum number of error responce (wready & rvalid) when AxLEN = 15?

    Does it need to respond 16th? or we can respond 1 only?

    Regards,

    -GARO

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    • over 5 years ago
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  • About AXI4 address channel and data channel handshake sequence

    田永丰
    田永丰

    I wonder whether the read/write data channel handshake must occur or assert after the address channel handshake completed?

    For example the master device will wait ARREADY assert or ARVALID dessert, before assert the RREADY?

    Remark:

    Just now, I noticed that…

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    • over 6 years ago
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  • Significance of the WVALID signal in AXI

    Ronnie Dominic Joseph
    Ronnie Dominic Joseph

    In AXI, does the rising and falling edge of the WVALID signal signify the start and end of a write burst? Can the WVALID signal go low before the write request for all the transfers in that burst are issued?

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    • over 6 years ago
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  • AXI FIXED burst ; Wr/Rd narrow transactions.

    Tsach
    Tsach

    1. I'm examining AXI burst of FIXED type.

    2. Data bus width is of 128bit.

    3. case scenario WRITE:

        awlen    = 2 (3 write transfers)

        awsize  = 2 (32bit per each transfer)

        awburst = 0 (FIXED)…

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    • over 6 years ago
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  • MakeUnique Transaction (ACE protocol)

    Rakesh Reddy
    Rakesh Reddy

    Hi.,

    As we know that there is a MakeUnique transaction in ace protocol, can anyone tell me how we can initiate this transaction..? I mean what is the respective signal in AXI4/ACE that allows us to set a master to initiate this MakeUnique transaction.…

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    • over 6 years ago
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  • Hi, regarding AXI wrte strobe functionality...

    Tsach
    Tsach

    I'm trying to understand the write strobe functionality for a 128bit bus width, burst type FIXED.

    Case scenario:

    AXI bus width 128bit.

    awlen    = 3 (4 write transfers)

    awsize  = 2 (32bit per each transfer)

    awburst = 0 (FIXED)

    awaddr…

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    • over 6 years ago
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  • Are there any restrictions for the width of an address signal in an AXI4 interface?

    Martin Stolpe
    Martin Stolpe

    Hello,

    in the AXI4 specification I didn't find anything mentioned about width restrictions for the address signal. I'm currently trying to simulate a component which I wrote in VHDL which provides an AXI4 Slave interface. The BFM I'm using to simulate…

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    • over 6 years ago
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  • In read or write transaction in AXI.what happen if data transaction  is before address.

    Rajesh Pandey
    Rajesh Pandey

    HI there,

    I have question regarding transaction in AXI4 bus (or any other bus). What happens  in write any read action when data transaction (handshaking) occurs before  address  transaction (handshaking) ?

    Will the data be written to the…

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    • over 6 years ago
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  • How does128Byte WriteLineUnique transaction map to a cache with 64Byte cache line size?

    Hanan
    Hanan

    Hello,

    I have an IP with an ACE-Lite I/F which can issue a 128Byte write transaction with a "WriteLineUnique" type. I  the system there will be a cortex A7 master(64bytes cache line). My question is: in case of such transaction (WriteLineUnique with 128bytes…

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    • over 6 years ago
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  • AXI Write Access: WLAST/WVALID handling

    sxuser
    sxuser

    Can I set WLAST high while WVALID is low? The AXI specification is not clear at this point.

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    • over 6 years ago
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  • AXI4 - read data interleaving

    Amit
    Amit

    Hi Folks,

    We need a clarification on Read Data Interleaving on AXI4

    Read Data Interleaving is supported in AXI4 and following is my understanding on Data Interleaving:

    Multiple Read commands can be executed simultaneously and data interleaving is supported…

    • Answered
    • over 6 years ago
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  • AXI Protocol -  Strobe Signal Value

    ramdhyani
    ramdhyani

    how to calculate the value of strobe signal in axi?

    • over 6 years ago
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  • AXI protocol - Unaligned data transfer definition

    ramdhyani
    ramdhyani

    IN axi,what is unaligned data transfer??

    • Answered
    • over 7 years ago
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  • How AXI addressing works for fixed burst with unaligned address.

    vikas verma
    vikas verma
    Please consider following example:

    Data bus width = 32 bit
    burst size = 4 bytes
    Burst length = 3
    Address = 0x02
    burst type = FIXED.

    Write strobes are high from byte address 0x02 to the last byte in this burst i.e. in first data beat 2 write strobes are high…
    • over 7 years ago
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  • Introduction to AXI Protocol: Understanding the AXI interface

    Christina Toole
    Christina Toole

    When part of a team, your group can become more capable than a single individual, but only if your team can work together and communicate effectively. Having members of a group talk over each other leads to nothing but a cacophony, and nothing gets done…

    • over 4 years ago
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  • New AMBA Specification Extends Security to Embedded Design: AMBA 5 AHB5

    Eoin McCann
    Eoin McCann

    The amount of data we generate is growing exponentially. Gartner has predicted that in 2015 the global mobile data traffic will be a total of 52 billion terabytes, an increase of 59 percent on 2014. It’s a staggering number that is driven not just by…

    • over 5 years ago
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