In the document AMBA3 AXI (3.2 Relationships between the channels)
Two relationships that must be maintained are:
• read data must always follow the address to which the data relates…
In the document AMBA3 AXI (3.2 Relationships between the channels)
Two relationships that must be maintained are:
• read data must always follow the address to which the data relates…
1/ WHY "the width of the ID field at a slave interface is wider than the ID field at a master
interface"??? Can you please explain in more detail the reason???
2/ Do AXI protocol have support "read interleaving"???
Thanks you so much…
I am a junior ASIC engineer. At the moment, I have three the question about AMBA AXI 3.0
1. No combination paths between master and slave, all timing path must be registered. Why the VALID and READY signals can assert in the same time ?
2. In the FIXED…
Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.
recently, i read "AMBA® AXI Protocol.pdf". but i have two questions about AXI after reading.
as you can see the first picture, slave send the read…
I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.
recently, i read "AMBA® AXI Protocol.pdf". but i have two questions about AXI after reading.
i wonder about interleaving and out-of order.
AXI supports…
Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.
Recently, I read "AMBA AXI Protocol.pdf". but i have two questions about AXI after reading.
Firstly, i very wonder AWID, WID and BID when write transaction…
Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.
recently, i read "AMBA® AXI Protocol.pdf". but i have three questions about AXI after reading.
firstly, i very wonder the handshake…
Can someone explain me the advantage of having decouple write address, data channels in AXI4?
In AXI3 with data interleaving we can have multiple masters sending data to various clients but in case of AXI4 we don't support interleaving so how decoupled…
HI,
Does anyone know the minimum number of error responce (wready & rvalid) when AxLEN = 15?
Does it need to respond 16th? or we can respond 1 only?
Regards,
-GARO
I wonder whether the read/write data channel handshake must occur or assert after the address channel handshake completed?
For example the master device will wait ARREADY assert or ARVALID dessert, before assert the RREADY?
Remark:
Just now, I noticed that…
In AXI, does the rising and falling edge of the WVALID signal signify the start and end of a write burst? Can the WVALID signal go low before the write request for all the transfers in that burst are issued?
1. I'm examining AXI burst of FIXED type.
2. Data bus width is of 128bit.
3. case scenario WRITE:
awlen = 2 (3 write transfers)
awsize = 2 (32bit per each transfer)
awburst = 0 (FIXED)…
Hi.,
As we know that there is a MakeUnique transaction in ace protocol, can anyone tell me how we can initiate this transaction..? I mean what is the respective signal in AXI4/ACE that allows us to set a master to initiate this MakeUnique transaction.…
I'm trying to understand the write strobe functionality for a 128bit bus width, burst type FIXED.
Case scenario:
AXI bus width 128bit.
awlen = 3 (4 write transfers)
awsize = 2 (32bit per each transfer)
awburst = 0 (FIXED)
awaddr…
Hello,
in the AXI4 specification I didn't find anything mentioned about width restrictions for the address signal. I'm currently trying to simulate a component which I wrote in VHDL which provides an AXI4 Slave interface. The BFM I'm using to simulate…
HI there,
I have question regarding transaction in AXI4 bus (or any other bus). What happens in write any read action when data transaction (handshaking) occurs before address transaction (handshaking) ?
Will the data be written to the…
Hello,
I have an IP with an ACE-Lite I/F which can issue a 128Byte write transaction with a "WriteLineUnique" type. I the system there will be a cortex A7 master(64bytes cache line). My question is: in case of such transaction (WriteLineUnique with 128bytes…
Can I set WLAST high while WVALID is low? The AXI specification is not clear at this point.
Hi Folks,
We need a clarification on Read Data Interleaving on AXI4
Read Data Interleaving is supported in AXI4 and following is my understanding on Data Interleaving:
Multiple Read commands can be executed simultaneously and data interleaving is supported…
how to calculate the value of strobe signal in axi?
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