• Problems about signal dependencies in AXI spec

    Yu-Hsin
    Yu-Hsin

    Hi,

    In AXI4/5 spec (IHI0022F), it listed a set of signal dependencies for read and write transactions.

    My problem is in Figure A3-7 AXI4 and AXI5 write transaction handshake dependencies. It noted that "Dependencies on the assertion of WVALID also require…

    • over 1 year ago
    • System
    • Embedded forum
  • AXI read response in error case

    Anupam Jain
    Anupam Jain

    Hi,

    In the AXI spec it is mentioned that , even in case of ERROR response, the slave needs to respond with the exact number of beats and indicate the response with each beat.

    Now my question here is if the response is going to be ERROR(lets say SLVERR…

    • over 1 year ago
    • System
    • Embedded forum
  • Why AXI4 changed the definition of AxCACHE?

    Yu-Hsin
    Yu-Hsin

    Hi,

    In AXI4, spec changed the definition of the definition of AxCACHE[3:2] from Write Allocate/Read Allocate to be Allocate/Other Allocate.

    But is there any concrete reason for this change? Actually I found some related statements from spec, but I couldn…

    • over 1 year ago
    • System
    • Embedded forum
  • Store operations where the cache line is already cached (ACE protocol)

    Vedant2611
    Vedant2611

    In Section C1.3 Channel Overview of the AMBA_AXI_and_ACE protocol specifications, It is mentioned under "Store operations where the cache line is already cached" as :

    The initiating master component requests a unique copy of the cache line…

    • over 1 year ago
    • System
    • Embedded forum
  • Removal of WID's in AMBA AXI4

    mvenkatesh
    mvenkatesh

    Hi ,

       What is the purpose of removing ID's (WID) in AXI4 ?

    If it because of reduction of pin count then We lost the " Write Data Interleaving" and "Out Of Order " Transaction features. Can you please tell me if any other reasons...(Arm Spec says.…

    • over 1 year ago
    • System
    • Embedded forum
  • Xen/dom0 on Juno

    Justin
    Justin

    Hey all,

    I have been playing around with Xen and Dom0 on a Juno r0 board. Currently dom0 is failing to initailize USB. This is an issue because the rootfs depends on the usb.

    usb 1-1: new high-speed USB device number 2 using ehci-platform

    usb 1-1: device…

    • Answered
    • over 4 years ago
    • Open Source Software and Platforms
    • Arm Development Platforms forum
  • AMBA Protocols (Specially AXI) frequency limit ?

    Smk417
    Smk417

    I wanted to ask about AMBA Protocols (Specially AXI) frequency limit ? Is there any upper limit for AXI4 of maximum operating frequency ? what is it ?

    • over 1 year ago
    • Open Source Software and Platforms
    • Arm Development Platforms forum
  • Partial Word Access to Altera Avalon Memory-Mapped Slave

    Qiangsheng Xiang
    Qiangsheng Xiang

    when I say partial word access, I mean 16-bit (two byte) or 8-bit (byte) read/write.

    Background:

    In one of our recent projects, Cyclone V SoC is used to replace 386 CPU in an existing product.

    I am responsible for the board and FPGA design. Another software…

    • Answered
    • over 4 years ago
    • System
    • SoC Design forum
  • why there is no split or retry responce in AXI ?

    Jay Zhao
    Jay Zhao

    In AHB, we have split and retry responce, but it doesn't exist in AXI, why ?

    • Answered
    • over 4 years ago
    • System
    • SoC Design forum
  • AXI narrow read with unaligned address

    jduarte
    jduarte

    Hi,

    I have a question about the correct behavior when performing a narrow read with an unaligned address; consider the following scenario:

    - 32 bit data bus

    - address x0001

    - length 0 (1 beat)

    - size 1 (2 byte)

    My interpretation of the spec is that in…

    • Answered
    • over 3 years ago
    • System
    • SoC Design forum
  • RMW operation on SRAM via AXI

    niket
    niket

    I am implementing Read Modified Write on SRAM through AXI. What is the role of awsize and wstrbe?

    Say data width is 64 bits, and awsize is set to support 64-bits, but the underlying wstrbe are only valid for lower 32-bits (8'b0000_1111). Does this candid…

    • Answered
    • over 3 years ago
    • System
    • SoC Design forum
  • AXI handshake between AW/AR-READY and B/R-RESP

    KalyanSuman
    KalyanSuman

    In AXI Write how the handshake between AW channel and B channel is taken care.

    Standard says that 

    "the slave must wait for both WVALID and WREADY to be asserted before asserting BVALID"

    Does that means BVALID will never be asserted in the same…

    • Answered
    • over 3 years ago
    • System
    • SoC Design forum
  • How does QoS with priority and ordering allowed with AXI ID?

    tarun4682
    tarun4682

    I have one question for QoS with AXI4:

    Can one master have multiple QoS values?

    Meaning one master issues requests with different QoS values but all with same AXI ID and the interconnect network arbitrates between these requests based on QoS value and…

    • over 3 years ago
    • System
    • SoC Design forum
  • ARM AXI4 protocol assertions trigger errm_wdata_num_prop5 and errm_wlast_stable quesitons

    armchronos
    armchronos

    Hi,

    I'm getting two AXI4 protocol assertion errors.

    For axi4_errm_wlast_stable, I can see why it's flagging an error but functionally it shouldn't be a problem.

    The WREADY =1 for one more cycle when though WVALID=0 and WLAST=0. 

    Is this a…

    • Answered
    • over 3 years ago
    • System
    • SoC Design forum
  • AXI modifiable read access

    arc
    arc

    The AXI protocol description states for modifiable transactions (ARCACHE[1] is asserted):

    "a read transaction can fetch more data than required"

    To me, this can be interpreted in two ways:

    1. The RVALID signal of the slave can be asserted for…
    • Answered
    • over 2 years ago
    • System
    • SoC Design forum
  • Project on AXI Bus.

    Naina
    Naina

    Hi,

    I am working on AXI bus for my college project. For my work I have to add something new in existing architecture. Can someone provide me idea for my work? 

    • over 2 years ago
    • System
    • SoC Design forum
  • unaligned address in AXI protocol

    dorababu
    dorababu

     i am sending data "NEWDATAA"  which is 8 bytes. and  starting address is 5, which is unaligned address then whether my data is loss or not . please explain how the whole transfer will happens. how the strobe will works. is my data start with aligned…

    • over 2 years ago
    • System
    • SoC Design forum
  • Further explanation needed for VAxQOSACCEPT, AWAKEUP, ACWAKEUP and SYSO*

    armchronos
    armchronos

    Hi ARM/arktos,

    Seems like this online discussion is not working properly.

    I ask a question, you reply, and if I reply the discussion tool doesn't echo back my reply by email.

    So most likely you may not see it.

    Below is my reply to your answer to my…

    • Answered
    • over 2 years ago
    • System
    • SoC Design forum
  • AXI4

    Vasu
    Vasu

    In the spec it is mentioned that AXI4 supports high-bandwidth, high-frequency and low-latency operation. How to justify this?  What is the meaning of bandwidth in this context? What are the  values of bandwidth and frequency? How they decide the operating…

    • Answered
    • over 2 years ago
    • System
    • SoC Design forum
  • AXI3 locked access

    Vasu
    Vasu

    I want to know what happens in these scenarios :
    1) Assume Master1 (M1) is doing locked access, if locked access fails before M1 does unlocking transaction what is the response to the M1?
    2) Assume M1 is doing locked transaction, if other Master2 (M2)…

    • over 2 years ago
    • System
    • SoC Design forum
  • AXI Burst Size meaning

    hayk
    hayk

    Dear Community,

    I am reading AXI speck from the ARM, please help better understand the AXI, by answering my questions regarding to Burst transaction.

    a)
    I cannot clearly understand the meaning of Burst size signals - ARSIZE and AWSIZE.
    When there are Bust…

    • over 2 years ago
    • System
    • SoC Design forum
  • Does CHI protocol interface use pipelines or register slice to support long distance connections ?

    armchronos
    armchronos

    Hi,

    I assume CHI needs to either pipeline or implement something like the AXI register slice to support long distance connections.

    Please confirm and where can I find relevant information for this topic.

    Thanks,

    David

    • over 2 years ago
    • System
    • SoC Design forum
  • AXI AHB APB quick reference cheat sheet

    MattHutson
    MattHutson

    Hi,

     I have tried to find a quick reference for AXI, AHB & APB to no avail, and after having to flit between the various documents and tables, I eventually created my own.

    So not sure of the legal ramifications of posting this elsewhere and whether…

    • over 2 years ago
    • System
    • SoC Design forum
  • AMBA AXI reset

    Sreekanth Reddy
    Sreekanth Reddy

    According to spec IHI0022D_amba_axi_protocol_spec  section A2.1 page number: A2-28

            "All signals are sampled on the rising edge of the global clock "

         Q) Should RESET_N also  be sampled on the rising edge only?

    Section A3.1.2,  says

       "The AXI protocol…

    • over 2 years ago
    • System
    • SoC Design forum
  • Can the ARM corrupt the timing on the AXI bus

    skbrown
    skbrown

    I have a Cyclone V SOC system, and the ARM is running Linux, and the FPGA is running SDI video and VIP suite items. The FPGA DDR memory is being used by the VIP suite and all works well. The ARM is using the DDR memory attached to it, and Linux does not…

    • over 1 year ago
    • System
    • SoC Design forum
<>