Getting started with AMBA and AMBA AXI

NickT

As you may be aware, far from being a misspelled fossilized tree resin, AMBA is a freely available open standard for the connection and management of functional blocks in a system-on-chip (SoC). Since the mid-90s, AMBA has been implemented by vendors…

AMBA AXI

SriGanesh

What is use of AWPROT and ARPROT signal in AXI? I meant the scenario where exactly it is used?

AMBA AXI Write response

Sai Krishna

I am just going through the specs of AMBA AXI.
I've few questions.It will be great if anybody clarify
1) Why there was no Write response for each beat in burst Write. But there is a seperate Read response for each beat in a Read burst ?
2) How to terminate…

over 6 years ago
System
SoC Design forum

applications of amba axi

abilash abilash

Note: This was originally posted on 7th February 2007 at http://forums.arm.com

hello, i have read the whole of the axi protocol. i would like to know the applications of the protocol. is it anywhere used in the real time applications or some specific devices…

over 6 years ago
System
SoC Design forum

AXI write strobes

jameskim jameskim

Note: This was originally posted on 21st February 2007 at http://forums.arm.com

the AXI spec says:

10.1 About unaligned transfers
[...]
For any burst that is made up of data transfers wider than one byte, it is possible that the first bytes that have to be…

over 6 years ago
System
SoC Design forum

AXI Read/Write ordering

Randy Pascarella

Note: This was originally posted on 24th October 2007 at http://forums.arm.com

Hello,
Section 8.6 of the AXI spec says that reads and writes have no ordering restrictions between them. It then says that if a RAW dependency exists, the master must wait…

over 6 years ago
System
SoC Design forum

More AXI write/read ordering

Randy Pascarella

Note: This was originally posted on 25th October 2007 at http://forums.arm.com

In another posting, a scenario given was with a RAW hazard where a bufferable write was followed by a read to an overlapping address. Sounds like the master's assumption upon…

over 6 years ago
System
SoC Design forum

AXI Cacheable vs. Bufferable

Randy Pascarella

Note: This was originally posted on 19th November 2007 at http://forums.arm.com

If an AXI slave acting as a bridge has accepted a bufferable (ACACHE[0]) and cacheable (ACACHE[1]) write and responded with BRESP, is it required to flush this buffered write…

over 6 years ago
System
SoC Design forum

AXI protocol

neha004

Note: This was originally posted on 30th December 2007 at http://forums.arm.com

Can anyone tell me the exact explanation and differnce between out of order completion and write data interleaving in detail...as i`m very confused with these terms

over 6 years ago
System
SoC Design forum

AXI locked access

spark spark

Note: This was originally posted on 29th May 2008 at http://forums.arm.com

Does a locked request on either the read or write channel cause both channels to be locked? For example, one master request a locked write transaction to a slave, the read channel…

over 6 years ago
System
SoC Design forum

the usage of WSTRB signal

Dong Luo

Note: This was originally posted on 26th February 2009 at http://forums.arm.com

Hi All,
I was going through the AMBA AXI specs, but I have some questions about the usage of the WSTRB signal. In the middle of a burst, can some bits of WSTRB be low? Again…

over 6 years ago
System
SoC Design forum

Write Data Interleaving - AXI

Amaresh Chaligeri

Note: This was originally posted on 19th March 2009 at http://forums.arm.com

Hello,

Can anybody help me to understand the reasoning behind write data interleaving ordering restriction imposed by AXI spec.
[Chapter 8.5 Write data interleaving]

"The order…

over 6 years ago
System
SoC Design forum

New Arm online training course: Introduction to the AMBA ACE protocol

NickT

Arm is pleased to announce a new online training topic - An introduction to the AMBA ACE protocol.

About the course

This training topic covers essential information on Arm’s AMBA ACE protocol. Hardware system-level coherency enables the sharing of…

10 months ago
Processors
Processors blog

AMBA

VT

Hello....!!!

Can anyone tell the minimum and maximum frequency or bandwidth on which AMBA AHB, APB, AXI and CHI and ACE can work successfully?

Answered

Bare Metal Input/Output - Documentation?

Mike Clark

Does anyone know of an Idiot's Guide to this topic? In particular, how does a processor with no special I/O instructions issue a request, e.g. to a serial output device to output "Hello, World"? And how does Memory-Mapped I/O work in detail? Where is…

Answered

AXI4: Wider transactions than BUS width allowed?

Robert Schilling

Hi AXI-experts,

Does AX4 support burst sizes larger than the bus width?

Narrow transactions are allowed, but do wider transactions also work?

Best regards,

Robert

hi. i wonder Register Slice of AMBA 3.0 AXI

In-Gyu.Lee

Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

Recently, i read "AMBA® AXI Protocol.pdf". but i have three questions about AXI after reading.

Register slice is described in AMBA 3.0 AXI.

"This makes…

Answered

AMBA AXI :Unaligned "INCR" data transfer

Kousik

Hi,

i am confusing in the following point ,with an example....

if

Start_Address = 23

Number_Bytes = 8

Burst_Length = 8

data_Bus_Byte…

Answered

STM(System Trace Macrocell)

dudu8

Can i observe the 1KB data that it is written over the STM AXI interface from STM ATB BUS ?

what i mean is that i want to send a 1KB data from STM AXI and observe it from the STM ATB with MIPI STPv2 format.

over 3 years ago
System
SoC Design forum

AXI4 Lite handshake

Long John

Hi,

in the AMBA/AXI Protocol specification, I read

There must be no combinatorial paths between input and output signals on both master and slave interfaces.

What signals, explicitly, may not have combinatorials between them?

Thanks in advance.

Answered

AXI3 write data interleaving with same AWID

mveereshm622

This is regarding the AXI3 write data interleaving. I understand how the write data interleaving works when AWID=WID when a slave is accessed by multi masters or a single master which can generate multiple outstanding transactions. But I have a query on…

Answered

over 1 year ago
System
SoC Design forum

boundary concept

maitry

Hi all,

I am new to protocols AHB and AXI.

can anyone explain why there is 4kb boundary in AXI and why there is 1 kb boundary in AHB?

Also what these boundaries are for? Does they represent the maximum slave size?

over 1 year ago
System
Embedded forum

Transfer size in AMBA AXI

subhajit02

Hi, I am not so clear about the concept of transfer size in AMBA AXI. My question is how to calculate wrap_boundary in wrap based data transfer when Number_Bytes (The maximum number of bytes in each data transfer) is changing in each transfer within a…

over 2 years ago
System
Embedded forum

AXI-4 questions

SBR_123

Hello,

I am pretty new to AMBA protocol and I am specifically interested in AXI-4. I have a few fundamental questions related to AXI-4 and I would appreciate if anyone can answer these.

1) I would like to know how read and write address requests issued…

Answered

over 4 years ago
System
Embedded forum

AMBA AXI CACHE

srp

i am not able to understand working of this CACHE signal pleas explain with simple example.

thank you!

over 2 years ago
System
Embedded forum