As you may be aware, far from being a misspelled fossilized tree resin, AMBA is a freely available open standard for the connection and management of functional blocks in a system-on-chip (SoC). Since the mid-90s, AMBA has been implemented by vendors…
Error in AMBA 5 CHI spec?
P189, 5.2.1 Dataless transaction without memory update
Why does RN-F0 transition I->UC, rather than UCE or UD? After MakeUnique, RN-F0 has obtained the right to modify the cache line by discarding all other copies, dirty or not, in other caches. The purpose…
- over 1 year ago
- System
- SoC Design forum
Hazard conditions in CHI
In chapter 4.9.2 At the ICN(HN-F) node CHI specification talks about what ICN should do when there is hazard condition. It says:
One example of these rules is chapter 5.6.1 CopyBack-Snoop hazard at RN-F, Figure 5-22 CopyBack-Snoop hazard at RN-F exa…
- over 1 year ago
- System
- SoC Design forum
How to understand Exclusive Transaction failure conditions in CHI?
The purpose of Exclusive Access is to read, calculate and modify a cache line atomically. The built-in Atomic Transactions can do some basic calculations at ICN or SN, but if more complex operations are necessary, Exclusive Access is needed.
CHI specification…
- over 1 year ago
- System
- SoC Design forum
What is AMBA?
I had just joined Duolog as a graduate of business through a graduate development program which links graduates with small to medium Irish enterprises. My role there was to expand their marketing reach in the competitive marketplace, but with no technical…
- over 5 years ago
- Processors
- Processors blog
What is AMBA 5 CHI and how does it help?
At last the time has finally come when I can talk about AMBA 5 - the next generation of ARM interface standard.
So, what's new?
To start this discussion it is worth answering a question I frequently get asked, which often goes along the lines of…
- over 6 years ago
- Processors
- Processors blog
Synopsys supports launch of Arm AMBA 5 AXI5, ACE5 protocols with 1st source code test suite and VIP
Through a blog post by Jeff Defilippi, Arm has just announced the new Arm AMBA 5 AXI5, ACE5 and ACE5-Lite protocols; you can request the the latest AMBA 5 specs through a link in that blog. These protocols are employed by Arm's latest technology, including…
- over 2 years ago
- Processors
- Processors blog
Introducing the next generation of AXI and ACE protocols
Arm is happy to announce the release of the next generation of AMBA 5 ACE5 and AXI5 protocols. A number of capabilities have been added over the prior AMBA 4 generation to align with AMBA 5 CHI. The protocols have been implemented in Arm’s latest technology…
- over 2 years ago
- Processors
- Processors blog
Introducing AMBA 5 CHI protocol enhancements: Specification now available
In 2013 Arm announced the AMBA 5 CHI protocol to provide the performance and scale required for infrastructure applications such as networking and data center. The protocol has been highly successful and has been the foundation for Arm many core systems…
- over 3 years ago
- System
- SoC Design blog
How do AMBA, CCIX and Gen-Z address the needs of the data center?
Interconnects and open standards have been a hot topic lately. A couple of weeks ago, Arm announced the CoreLink CMN-600 Coherent Mesh Network and CoreLink DMC-620 Dynamic Memory Controller IP, which support AMBA 5 CHI, the open standard for high performance…
- over 3 years ago
- Processors
- Processors blog