Hi All,

I have a question about assert timing of PSTRB and PPROT.

I think APB4 spec (IHI0024C_amba_apb_protocol_spec.pdf) does not describe when PSTRB and PPROT should be asserted.
I guess these signals should be asserted while PSEL is high like PADDR…

In case of readunique transaction cache line is copied into the initiating master's cache(whether it is clean or dirty) and invalidated in snooped master's cache and then store operaation is performed in initiating master's cache line.

In…

In Section C1.3 Channel Overview of the AMBA_AXI_and_ACE protocol specifications, It is mentioned under "Store operations where the cache line is already cached" as :

The initiating master component requests a unique copy of the cache line…

PSTRB signal indicates which byte lanes to update during a write transfer.

it shows that the bus contain valid data, when PSTRB[3:0]=1111.

why we need bus instead of single bit PSTRB signal?