Hi,

In AMBA AHB:-

     For two clock cycle SPLIT or RETRY response, hgrant must be low after 1st clock cycle of SPLIT or RETRY response.

   q)  For two clock cycle ERROR response, is it mandatory of hgrant must be low after 1st clock…

What would happen if HREADY will be lower not after address phase, but according to HW internal logic that wants to hold CPU for some clock cycles.

Thanks

I am a Digital Verification Design Engineer.

Currently, I am in the process of developing an UVM Test Bench for AHB 2.0.

I have following questions.

1) From AHB Master side, Can BUSY cycles be inserted in middle of INCR16 burst?

2) From AHB Master side,…

Why the address boundary for AHB burst should not cross 1KB??

And in case of burst operation, is that every beat the address increment taken care by master?

Can the AMBA AHB Slave give multiple SPLIT response again to the AHB Master that has been given SPLIT response before and after updating hsplit signal for that Master by the Slave?

Hi ,

In AHB specs, There is one note as below.

Note

Every slave must have a predetermined maximum number of wait states that it will insert before it backs off the bus, in order to allow the calculation of the latency of accessing the bus. It is recommended…

Hi,

   I have a question on AMBA AHB, Let us assume we are firing INCR4 burst from master M1.

  Let us assume  EBT is happened during 2nd transfer address phase of INCR4 burst (i.e Master M1 lost its grant without driving of its data phase and…

Hello....!!!

Can anyone tell the minimum and maximum frequency or bandwidth on which AMBA AHB, APB, AXI and CHI and ACE can work successfully?

The spec simply states that a master may cancel a burst after receiving an ERROR response for one of its transfers or continue with the remaining transfers.

The spec does not go on to state what the slave is supposed to do in that case though. Should it…

Hello everyone,

Please describe me the transfer continuation process after ERROR response from the slave.

As shown in the above figure at cycle T4 if MASTER identifies the ERROR response from the SLAVE. Now, if the MASTER wants to continue the current transfer…

Hello everyone,

I want to understand the transfer continuation process from AHB MASTER during ERROR response from AHB SLAVE.

As specified in the AMBA Specifications (Rev 2.0) IHI0011A_AMBA_SPEC.pdf section 3.9.4 page no 3-23 :

3.9.4 Error response

If a slave…