• New Arm online training course: Introduction to the AMBA ACE protocol

    NickT
    NickT

    Arm is pleased to announce a new online training topic - An introduction to the AMBA ACE protocol.

    About the course

    This training topic covers essential information on Arm’s AMBA ACE protocol. Hardware system-level coherency enables the sharing of…

    • 10 months ago
    • Processors
    • Processors blog

  • AXI4: Wider transactions than BUS width allowed?

    Robert Schilling
    Robert Schilling

    Hi AXI-experts,

    Does AX4 support burst sizes larger than the bus width?

    Narrow transactions are allowed, but do wider transactions also work?

    Best regards,

    Robert

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum

  • ACE-Lite Master and Slaves

    Uma
    Uma

    Hello Ashley,

          I have couple of basic doubts w.r.t ACE-Lite Slave.

          The AMBA spec for ACE-Lite says that " ACE-Lite is used by master components that do not have hardware coherent caches". But they can issue transactions…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum

  • ACE5 / ACE5 Lite questions for ARBAR/AWBAR, AWSTASH*, and BROADCAST* signals

    armchronos
    armchronos

    Hi,

    1) ARBAR/AWBAR

    These two signals are mentioned : ARBAR, AWBAR but in the AMBA5 spec F2.1 Signal Matrix, these signals are listed as "N" (must not be present), page 419 and 420 of 440 pages. 

    So are these signals used on the ACE5 interface…

    • Answered
    • over 2 years ago
    • System
    • SoC Design forum

  • CHI/ ACE-Lite Interface

    Sidhaarth
    Sidhaarth

    I have a custom accelerator to be integrated with Corelink CMN-600. The CMN-600 has a CHI/ ACE-Lite Interface. How can I add a CHI/ ACE-Lite Interface to my custom accelerator? Is there a tool which can generate the RTL for CHI/ ACE-Lite?

    • over 1 year ago
    • System
    • SoC Design forum

  • Extended System Coherency: Part 1 - Cache Coherency Fundamentals

    Neil Parris
    Neil Parris

    Chinese Version 中文版：扩展系统一致性 - 第 1 部分 - 缓存一致性基本信息

    Introduction

    The theme of TechCon 2013 was “Where intelligence connects” and in many ways hardware system coherency is an important part of connecting the intelligence of an SoC. This year I presented…

    • over 6 years ago
    • Processors
    • Processors blog

  • How does128Byte WriteLineUnique transaction map to a cache with 64Byte cache line size?

    Hanan
    Hanan

    Hello,

    I have an IP with an ACE-Lite I/F which can issue a 128Byte write transaction with a "WriteLineUnique" type. I  the system there will be a cortex A7 master(64bytes cache line). My question is: in case of such transaction (WriteLineUnique with 128bytes…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum