• New Arm online training course: Introduction to the AMBA ACE protocol

    NickT
    NickT

    Arm is pleased to announce a new online training topic - An introduction to the AMBA ACE protocol.

    About the course

    This training topic covers essential information on Arm’s AMBA ACE protocol. Hardware system-level coherency enables the sharing of…

    • 10 months ago
    • Processors
    • Processors blog

  • Cache type and cache operation sequence

    sd
    sd

    I have a shared memory in DDR  --- shared between two separate ARM execution environments (say A and B)  in a heterogeneous compute SoC.

    SW on each execution units (A and B) Reads and Writes to this shared location (imagine a array/matrix that…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum

  • SC and SD states in case of ReadNoSnoop transactions

    Vaibhav Chavan
    Vaibhav Chavan

    Hi All,

    This question is regarding "ReadNoSnoop" transaction of AMBA- ACE protocol.

    If "ReadNoSnoop" transaction is used in a region of memory that is not shareable with other masters, then how can the cache line have have "Shared Clean" or "Shared…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum

  • Bare Metal Input/Output - Documentation?

    Mike Clark
    Mike Clark

    Does anyone know of an Idiot's Guide to this topic? In particular, how does a processor with no special I/O instructions issue a request, e.g. to a serial output device to output "Hello, World"? And how does Memory-Mapped I/O work in detail? Where is…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum

  • AXI4: Wider transactions than BUS width allowed?

    Robert Schilling
    Robert Schilling

    Hi AXI-experts,

    Does AX4 support burst sizes larger than the bus width?

    Narrow transactions are allowed, but do wider transactions also work?

    Best regards,

    Robert

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum

  • ACE protocol : Eviction and snoop request at same time

    Chakri Myneni
    Chakri Myneni

    How to handle below scenario ?

    • At time t1 let us suppose L1 data cache is evicting a line and write address is sent on write address channel by asserting AWVALID (AWREADY is high)
    • At same time t1, there is a snoop request from interconnect on snoop address…
    • Answered
    • over 1 year ago
    • System
    • SoC Design forum

  • barrier instructions Vs. barrier transactions

    zyto
    zyto

    I have several questions about barrier operarions.

    1. how to operate barrier instructions ISB, DMB, DSB in ACE?

         a) when ISB is executed, what are the signal values about barrier transaction  (AxBAR, AxSNOOP , AxDOMAIN)?

       …

    • over 6 years ago
    • System
    • Embedded forum

  • Cache Maintenance Transactions

    Taniya Garg
    Taniya Garg

    Hi,

    I am reading ACE protocol and i am confused about when to use cache maintenance transactions. On what basis should i decide when to use cache maintenance transaction and which transaction to be used?

    Can anyone please help?

    • over 1 year ago
    • System
    • Embedded forum

  • How to handle Cache flush in ACE?

    Taniya Garg
    Taniya Garg

    Hi,

    I want to know which transaction should be issued by ACE interface on the channel when a flush/clean request is being processed by the cache?

    Can anyone please help.

    Regards,

    Taniya Garg

    • over 1 year ago
    • System
    • Embedded forum

  • What's the purpose for WACK and RACK for ACE and what's the relationship with WVALID and RVALID ?

    armchronos
    armchronos

    Hi,

    From hardware perspective, what's the purpose of WACK and RACK and how does it affect the ACE protocol ?

    I can see that the specification says the master issues these two signals to indicate to the interconnect that Write and Read transactions…

    • Answered
    • over 2 years ago
    • System
    • SoC Design forum

  • Please explain some of the new ACE5 signals in relation to the MASTER and INTERCONNECT behavior

    armchronos
    armchronos

    Hi,

    The AMBA5 spec for ACE5 shows some new signals versus ACE4 :

    VAWQOSACCEPT

    VARQOSACCEPT

    AWAKEUP

    ACWAKEUP

    SYSCOREQ

    SYSCOACK

    How are these used in an SOC system ?

    For example, I think but I'm not usre if VAWQOSACCEPT, VARQOSACCEPT is output by each slave…

    • Answered
    • over 2 years ago
    • System
    • SoC Design forum

  • Further explanation needed for VAxQOSACCEPT, AWAKEUP, ACWAKEUP and SYSO*

    armchronos
    armchronos

    Hi ARM/arktos,

    Seems like this online discussion is not working properly.

    I ask a question, you reply, and if I reply the discussion tool doesn't echo back my reply by email.

    So most likely you may not see it.

    Below is my reply to your answer to my…

    • Answered
    • over 2 years ago
    • System
    • SoC Design forum

  • ACE5 / ACE5 Lite questions for ARBAR/AWBAR, AWSTASH*, and BROADCAST* signals

    armchronos
    armchronos

    Hi,

    1) ARBAR/AWBAR

    These two signals are mentioned : ARBAR, AWBAR but in the AMBA5 spec F2.1 Signal Matrix, these signals are listed as "N" (must not be present), page 419 and 420 of 440 pages. 

    So are these signals used on the ACE5 interface…

    • Answered
    • over 2 years ago
    • System
    • SoC Design forum

  • AXI read transfer

    vidya
    vidya

    If the slave is not able to process read request from master, which response is expected from slave?

    • Answered
    • over 3 years ago
    • System
    • SoC Design forum

  • ACE - ReadNoSnoop transaction

    parita
    parita

    In ACE Specifications - ARM IHI 0022E, in ReadNoSnoop transactions how is the following other state of cacheline

    given on page number C4-197 transaction permitted :

    Start State  - ShareClean

    RRESP[3] - 0, RRESP[2] - 0

    End State - Invalid or UniqueCl…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum

  • MakeUnique Transaction (ACE protocol)

    Rakesh Reddy
    Rakesh Reddy

    Hi.,

    As we know that there is a MakeUnique transaction in ace protocol, can anyone tell me how we can initiate this transaction..? I mean what is the respective signal in AXI4/ACE that allows us to set a master to initiate this MakeUnique transaction.…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum

  • 扩展系统一致性 - 第 3 部分 - 性能提升和 CoreLink CCI-500 简介

    Song Bin 宋斌
    Song Bin 宋斌

    原文地址：Extended System Coherency - Part 3 – Increasing Performance and Introducing CoreLink CCI-500

    原作者:neilparris

    在本周，我们宣布推出旨在增强高端移动体验的全新 IP 套件。 此套件的核心是 ARM CoreLink CCI-500 缓存一致性互联，它以率先获得市场成功的上一代互联为基础，拓展了 ARM 系统在性能和更低功耗上的领先地位。

    一年前我发表了与本主题相关的第一篇博文，…

    • over 5 years ago
    • 中文社区
    • 中文社区博客

  • 扩展系统一致性 - 第 2 部分 - 实施、big.LITTLE、GPU 计算和企业级应用

    Song Bin 宋斌
    Song Bin 宋斌

    原文地址： Extended System Coherency - Part 2 - Implementation, big.LITTLE, GPU Compute and Enterprise

    原作者：neilparris

    本文是关于硬件一致性系列博文中的第二篇。 在第一篇博文中，我介绍了缓存一致性的基本信息： 扩展系统一致性 - 第 1 部分 - 缓存一致性基本信息

    此部分探讨硬件缓存一致性的实施和用例。

    另有一个详述 CoreLink CCI-500 的第 3 部分： 扩展系统一致性 - 第 3

    …
    • over 5 years ago
    • 中文社区
    • 中文社区博客

  • 扩展系统一致性 - 第 1 部分 - 缓存一致性基本信息

    Song Bin 宋斌
    Song Bin 宋斌

    原文地址：Extended System Coherency - Part 1 - Cache Coherency Fundamentals

    原作者：neilparris

    简介

    TechCon 2013 的主题是“智能互联”，而在许多方面，硬件系统一致性是 SoC 中智能互联的一个重要部分。我在今年的演讲“移动等平台的扩展系统一致性”中介绍了缓存一致性的基本信息，探讨了相关实施，也研究了一些用例。 本文是系列博文中的第一篇，首先介绍缓存一致性的基本信息。

    …
    • over 5 years ago
    • 中文社区
    • 中文社区博客

  • AMBA 4 ACE and Hardware Cache Coherency - Top 5 Questions

    Neil Parris
    Neil Parris

    I thought I'd post a short blog post about commonly asked questions on AMBA 4 ACE and system coherency.

    What does ACE mean?

    ACE is the "AXI Coherency Extensions" introduced with the AMBA 4 specification released in 2011. For those of you thinking "What…

    • over 6 years ago
    • Processors
    • Processors blog

  • big.LITTLE and AMBA 4 ACE keep your cache warm and avoid flushes

    Neil Parris
    Neil Parris

    Updated 29th October 2013


    High performance and power efficiency are critical to the latest mobile devices, and AMBA® 4 ACE™ is a fundamental technology supporting ARM's big.LITTLE processing. In case you missed the announcements, the big…

    • over 6 years ago
    • Processors
    • Processors blog