Is it possible for a CHI Node to receive an L-Credit Return when in RUN State? 

Hi All,

I have a question on AMBA5 AHB feature : Stable_between_Clock property

The AMBA5 AHB Specification describes:

Signals that are described as being stable are required to remain at the same value when sampled at different rising clock edges in an…

Hello,

i didnt find at spec any note about the waited write transfer.

for example 

T1 : NONSEQ + write transfer  + HREADY is high

T2: HREADY dropped + HTRANS is idle - HWDATA ?

does the HWDATA have to be the right data or it can be any junk ? and only when…

1. How barrier instructions like `dmb ishld` and `ldar/stlr` translate to ACE barrier transactions?

I am curious about how barrier instructions which will only affect specific types of memory operations would translate to ACE barrier transactions.

I supposed…

Hi,

As indicated in few previous answers (Link Given below) on the big-endian, I believe that the big-endian type in AHB-Lite Spec is BE32. And further the AHB5 Spec added another type of big-endian as BE8. Hence, the active byte lanes for a 32-bit big…

Hello to all,

I have a question about AMBA3 AHB-Lite and AHB5 Specification:

In AMBA3 AHB-Lite Specification, "Table 6-2 Active byte lanes for a 32-bit big-endian data bus" is mean word-invariant big-endian or byte-invariant big-endian? Why its…

Hi all~

I have some questions about AHB5 specification

1.If CPU(or another slave) is in 32-bit single-copy atomic group, can I only write/read a byte to it ? (HWDATA/HRDATA is 32bit-width, HBUST=SINGLE, HSIZE='b000)

2.What is the description "…

Can somebody please explain how barrier transactions in ACE work?

Thanks in advance.

Hi,

The AMBA5 spec for ACE5 shows some new signals versus ACE4 :

VAWQOSACCEPT

VARQOSACCEPT

AWAKEUP

ACWAKEUP

SYSCOREQ

SYSCOACK

How are these used in an SOC system ?

For example, I think but I'm not usre if VAWQOSACCEPT, VARQOSACCEPT is output by each slave…

Hi ARM/arktos,

Seems like this online discussion is not working properly.

I ask a question, you reply, and if I reply the discussion tool doesn't echo back my reply by email.

So most likely you may not see it.

Below is my reply to your answer to my…

Hi All,

                           I have doubt in ahb_lite hresp signaling when the address phase is extending.

In the following diagram transfer address c is extending because of data phase of B.

In 3rd clk cycle address C is sampled so that shall we expect the…