I'm working with the obsfucated RTL for Cortex-M3. I have a working design that muxes the 3 AHB-lite buses to 2 AXI3 buses. This design is analogous to the Xilinx designstart design with a code bus and a system bus. The processor correctly boot from the…

Hi,

Can someone clarify below queries I have wrt AHB-Lite,

1. Is there any relation between HTRANS=IDLE and hready ? Like,
   1. Whenever IDLE comes hready is de-asserted (or)
   2. Whenever hready is de-asserted, master gives IDLE
2. What is the maximum duration…

Hi, AHB-newbie here.

For AHB-lite is there any way that the Slave may signal to the Master that it is not ready to accept any transactions? 

Driving HREADY low only extends the data phase of the current transaction.

My understanding that the MASTER always…

In AHB-Lite cases, every transfer starts with address phase with signals from master.

And also in multi-master cases, arbiter decides with whether it can GRANT bus access to other masters or not.

So, I think it's fine to only let masters or arbiters to…

Hi,

In spec it's mentioned that in WRAP transaction the un-aligned address will be made aligned but only when it's crossing the boundary.

Wanted to know what's expected when the WRAP txn is started with a un-aligned address.

Case1: Starting…

The transfers in AHB protocols occur in two phases - address phase and data phase. Does this mean that the processor (Master) must have pipelined architecture?

I've understood how it works and what happens in it, but  what is the use of having a wrapping bursts? What are some scenarios where it provides an edge?

This is more of a conceptual doubt than a doubt in protocol. I've come across many papers where state machines are designed for AHB and AHB-Lite. I never understood why a state machine is required and where exactly is it incorporated(inside the processor…

Currently, the processor has simple load store architecture and is directly connected to the external memory without any bus interface. For the sake of uniformity, I'm implementing the AHB-Lite Bus Architecture for this system. The processor by design…

I am not able to see any visible improvements due to the BURST transfers. The same BURST transfer could be done through multiple SINGLE transfers, in the same number of cycles. Then what is te advantage of having BURST transfers?

Hello to all,

I am trying to figure out the variation in current consumption as well as in clock cycles due to different memory regions and different offsets. During various experiments, I have found the following results:

LDR R4,[R1,#0x0]  (R1 = 0x00000000…

HI...

A)

     1). I am now using a continuously 10 transfer of the SINGLE BURST write based read transfer. In spec says the default ready signal is HIGH.

     2).First thing i complete the first transfer of the write based read operation.

    3). Then it takes…

HI 

     I am using a single transfer in ahb lite in wait state.First i am write till htrans will maintain or not.

    If i am using a write based read ,The write is not complete due to wait at the time ,At the time again i put a same addr in read transfer…

Hi All,

               Consider the following burst transfers.

1. INCR4 (WR) IDLE INCR4(RD)

2. INCR4 (WR) INCR4(RD)

3. INCR4 (WR - WR1 ,WR2, IDLE, WR3 ,WR4 )   INCR4(RD)

             All the above transactions are valid transfer or not .

Can we trigger multiple burst…

Hello to all,

I have a question about AMBA3 AHB-Lite and AHB5 Specification:

In AMBA3 AHB-Lite Specification, "Table 6-2 Active byte lanes for a 32-bit big-endian data bus" is mean word-invariant big-endian or byte-invariant big-endian? Why its…

Hello to all AHB experts,

I have some question about AHB-Lite interconnection.

If I want to build 2 masters share 1 slave systems. I add a arbiter in the interconnect circuit, so that only one master could access the slave at a time.

My question is how…

Hi

I am a rookie part of a group working on building a Microcontroller, for which we've decided to use AHB Lite protocol with one single master for interconnection. I have thoroughly examined the protocol and am well versed in its behaviour. Our idea…

Hi All,

                           I have doubt in ahb_lite hresp signaling when the address phase is extending.

In the following diagram transfer address c is extending because of data phase of B.

In 3rd clk cycle address C is sampled so that shall we expect the…

Hi All ,

                      The following figure shows the INCR4 burst transaction.

Here the address increment is happening in each clk cycle  As per AHB protocol Single outstanding address is allowed.

What are the possible adjustment has to be made for this transaction…

Hi,

 I am developing a RTL code for AHB lite - AXI bridge. I want to understand what are the possible error scenarios in AHB?

1.I can think of invalid address as the only case. Is there any other scenario?

2. I am performing a INCR4 transfer on AHB side…

Hello,

 what are the additional features added or removed in AHB lite;

regards

Pavan