• multiple definition of `__stack_chk_fail'

    Alexandre Gonzalo
    Alexandre Gonzalo

    Hi,
    I am trying to migrate GCC from 7.2.1 to 8.3.
    To do so, I took the prebuilt binaries from your website
    developer.arm.com/.../downloads

    I used to take the packages from Linaro in the past.
    I am using the bare metal binaries for AArch64.
    I have the following…

    • over 1 year ago
    • Open Source Software and Platforms
    • GNU Toolchain forum
  • MPIDR and affinity

    Tony201900
    Tony201900

    Hi there,

    I am learning AARCH64 and would like to know about the mpidr_el1 register and affinity levels. I have read the relevant sections in the programmer's guide but I am just not able to understand it.

    my questions:

    how does the OS know on which…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • How could I find the critical functions when dual core cpu is fully loading?

    Myles
    Myles

    It can see almost 100% CPU0 usage during the timeline 2.34s ~ 2.42s(in figure 1). How can we know which functions are executed in CPU0/ CPU1 @timeline 2.376s(in figure 2)?

    The figure 3 is show the functions sheet @timeline 2.376s, but no more information…

    • Answered
    • over 1 year ago
    • Software Tools
    • Arm Development Studio forum
  • How many people develop on a laptop with Linux?

    Richard Henwood
    Richard Henwood

    I've been a huge fan of Linux for many years. I have been fortunate to have it as my primary development platform as it has morphed from a workstation to a laptop. Today, you can buy a Lenovo Yoga C630 laptop/tablet with Windows 10 and 8GB of RAM. I…

    • over 1 year ago
    • Processors
    • Processors blog
  • New developer guides for AArch64

    Martin Weidmann
    Martin Weidmann

    We (Arm's Support and Content Services teams) have been working on creating a Developer Guide for AArch64.  They're aimed at anyone wanting a bare-metal focused introduction to the Armv8-A architecture.  The first few chapters are now live, with…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • Affordable arm tools for Assembly or C code for ARM-32 and 64

    br-dev
    br-dev

    Hi,  i am developing allways opensource code as home hobbies. I have a mac OS and  many ARM cortex mainly on RPBI. I use to code GCC but i am now going to SIMD and i am thinking to have a proper dev env. what could you suggest. I can invest in a NUC for…

    • over 1 year ago
    • Open Source Software and Platforms
    • Arm Development Platforms forum
  • Optee OS compilation issue for Raspberry Pi 3 platform

    Manikandan Ramadass
    Manikandan Ramadass

    Hi Experts,

    I am trying to compile the Optee OS for Raspberry Pi 3 platform.It is 64bit aarch-linux-gnu.

    So i am giving the option like below for compilation but i am getting the compilation errors related to aarch32 and aarch64.

    make CFG_AARCH64_core…

    • over 1 year ago
    • Open Source Software and Platforms
    • Arm Development Platforms forum
  • aarch64 Exception Level Sw itch from EL1 to EL0

    michaelyuanfeng
    michaelyuanfeng

    Hi Expert,

    I am working on a simple kernel and test it on Qemu which supports RasPi3. During the boot level. Ras Pi goes to EL3 level, and I set spsr_el3 to 1 and elr_el3 to kernel_main and then use eret to enter EL1 mode. My problem is I create a kernel…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to use Cortex-a53 FVP for AArch32 platform in DS-5?

    ldivya47
    ldivya47

    Hi all,
    I have downloaded Cortex-A53 FVP (Version-10.2). I am able to run code on AArch64 platform in DS-5 simulator. How to use this Cortex-A53 FVP to run on AArch32 ? What are the required settings for this? Can anyone help me on this.

    Thanks,
    Divya.

    …
    • Answered
    • over 3 years ago
    • System
    • Embedded forum
  • LD_RETIRED , ST_RETIRED Events not working

    ldivya47
    ldivya47

    Hi,

    I am tyring to get load count , store count and instrucion count  in AArch64 DS-5 by using ARM64 PMU Events LD_RETIRED , ST_RETIRED and INST_RETIRED.

    I am able to get instruction count , but not load and store count, please find the code and enums i used…

    • Answered
    • over 3 years ago
    • System
    • Embedded forum
  • How to run AArch32 code in DS-5 AArch64?

    ldivya47
    ldivya47

    Hi,

    I installed DS-5 64-bit version in windows, but i received 32-bit code which is running on AArch32 without any issue , and it's not running on my machine with AArch64 DS-5, is there any setting which i can do to run the same code without any changes…

    • Answered
    • over 3 years ago
    • Software Tools
    • Arm Development Studio forum
  • Interrupt status in Aarch64

    uditknit
    uditknit

    Hello, 

    In Cortex, A9 CPU register CPSR tells the current execution mode , bit M[3;0]

    I am looking for if there is similar register present in A64 architecture . 

    Reading ESR_EL3/EL2/EL1, I think this is difficult to determine, if system in IRQ mode or…

    • over 3 years ago
    • System
    • Embedded forum
  • VMSAv8-64 -- worst-case effects of misprogramming of the Contiguous bit

    Olivier Delande
    Olivier Delande

    I would like to precisely understand the implications of misprogramming the Contiguous bit in VMSAv8-64 translation tables.

    I have a hypervisor running at EL2 in the AArch64 execution state, using two-stage memory translation for the guests. At some point…

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Is there any tools which can convert memory to assemble code?

    tao.zeng
    tao.zeng

     I am debugging in a Android problem. From log file there is a crash in services. But it is in service.odex. I tried to dump memory around crash pc and got values as following:

    [96941.575555@3] vma for d0936954:
    [96941.578614@3] d0578000-d0e05000 r-xp 00c90000…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • VMSAv8-64 - How to change 2-stage translation table descriptors of a given VMID and do invalidation afterwards?

    Jorge
    Jorge

    Hello everyone,

    Basically, I have a setup in which an hypervisor is running in EL2 and two guestOS running in EL1/EL0, being one a special guest (able to perform requests to the hypervisor), and the other one a limited guestOS. In ARMv8, each guest OS…

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cache Allocation Technology

    sarbojit
    sarbojit

    Hi guys,

    I have a question regarding "Cache allocation technology" that is present in Broadwell processors of Intel. Does ARM (aarch32/aarch64) support similar way of partitioning the LLC for a process to access?

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • A53 preload mechanism

    MarkL
    MarkL

    Hi,

    I am reading the A53 MP Core doc.

    My question is related to instruction preloading in aarch64.

    In case of a very large block of code with no function calls, I want to make sure the L1 cache is always filled.

    Question 1:  Will the PLI instruction first…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • luajit compilation on aarch64

    Bhanu
    Bhanu

    Hi,

       I am trying to build luajit on aarch64 platform. I have downloaded source from https://github.com/cbaylis/luajit-aarch64 .

      I am getting the below error when I compilled the source. 


    root@node:/root/luajit-aarch64-master# make
    ==== Building LuaJIT 2…
    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Does Aarch64 LDTR behave differently in secure vs non-secure?

    dcb56
    dcb56

    Can LDTR be used to test requests from secure EL0 or are all results taken in the context of NS EL0?

    • over 2 years ago
    • System
    • Embedded forum
  • System level Implementation of Generic Timer in Cortex A53

    Vasu
    Vasu

    Hi,

    Im new to ARM. Im learning generic timers in cortex a-53. I wanted to know whats the meaning of "system level implementation" of Generic Timer and "PE implementations" of the Generic Timer.  How is it different from Generic timer…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • indirect branches in ARMv8

    MarekBykowski
    MarekBykowski

    Please clarify that with me... With

    "The current Program Counter (PC) cannot be referred to by number as if part of
    the general register file and therefore cannot be used as the source or destination
    of arithmetic instructions, or as the base, index…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • which register are dedicated for each MPCore in ARMv8-A architecture?

    StanleyDDD
    StanleyDDD
    Hi  Expert,
    I'm a beginner to ARMv8-A architecture MPcore and now studying A35 MPCore processor documents for low-level software developing.
    One question, when I read DDI0487C_a_armv8_arm and DEN0024A_v8_architecture_PG, from my understanding, there…
    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Text section size for executable created with ARMCC 6.7 is more than expected

    Mubin
    Mubin

    Hi,

    I am porting Xilinx standalone drivers and libraries to armcc 6.7 compiler. I tried xilinx hello world application
    with the ported code base (for cortexa53 processor), and obseverd that text section size is ~82 KB. However, if i compile same hello…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • To run library functions on arm a53 core

    Sagar K
    Sagar K

    Hello experts,
    I am working on a53 core in which I am not able to run string library functions like memset, memcpy etc. I have included the string.h library also but it is generation an exception. The same code works on the a15 core without any modification…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Confusion about exception level of ARMv8

    Xinwei
    Xinwei

    Hi,

    I am fairly new to ARM processor and start work with cortexA57 recently.  After reading the technical manual and programmer guide , I have some questions regarding the exception level of v8.

    1. How does the exception level change from one to…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
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