• Which register excactly control the endiness in the EL0 data access? SPSR_EL1 or SCTLR_EL1?

    George_
    George_

    Hello:

    Suppose all exception Ievels support both big and little endian operation. According to the ARMv8 ARMARM, when exception taken from AArch32 state, the SPSR_EL1.E bit can control the endianess on executing an exception return operation in EL1, which…

    • 10 hours ago
    • Processors
    • Cortex-A / A-Profile forum
  • aarch64 instruction

    niuyf
    niuyf

    I have a build problem when use aarch64 instruction. I use ds5 for simulation,  

    target CPU: Generic ARMv8-A AArch64

    target FPU ARMv8(NEON & Crypto)

    others use default

    UMOV      w5, v3.h[#2]

    index #2 have 2 errors

    error: unknown token in expression

    error…

    • 5 days ago
    • Processors
    • Cortex-A / A-Profile forum
  • Tensorflow/Pytorch with GPU on ARM64

    Maciek
    Maciek

    Hi,

    I wish to launch some ML python scripts on arm64 and I have a question how one could use tensorflow or pytorch with gpu acceleration using nvidia drivers. As I can see, for ARM64 NVIDIA supports only CUDA 11. However tensorflow is only compatible…

    • 23 days ago
    • Open Source Software and Platforms
    • Machine Learning forum
  • Where to get, or how to build toolchain "aarch64 for aarch64 linux"? ? Error trying to build as in "release notes"

    iav
    iav

    Where to get, or how to build toolchain "aarch64 for aarch64 linux"?

    I try to do as described in ABE release notes:

    git clone https://git.linaro.org/toolchain/abe.git

    run ../abe/abe.sh --manifest gcc-arm-aarch64-none-linux-gnu-abe-manifest.txt…

    • 1 month ago
    • Open Source Software and Platforms
    • GNU Toolchain forum
  • Delay in aarch64-elf-gdb symbol parsing

    Ranjith
    Ranjith

    Hi All,

    When I try to parse the symbols using the latet aarch64-gdb from the arm website it is giving some unexpected delay during the symbol parsing.

    For example, if i execute "file filename.elf", it is taking 10-20 seconds to finish the operation.…

    • 3 months ago
    • Software Tools
    • Arm Compilers forum
  • How to download aarch64 corss compiler?

    gamecss
    gamecss

    I go to GNU Arm Embedded Toolchain,but only support 32-bin arm.

    I go to GNU Toolchain for the A-profile architecture,but version too old.

    • 4 months ago
    • Software Tools
    • Arm Compilers forum
  • Invalid Exception Class

    Killbox
    Killbox

    When debugging my bare metal app I'm getting an exception I don't understand.

    The processor is the Cortex-A53

    The Exception occurs on "str q0, [sp, #96]"

    When reading ESR_EL1 i get 0x1FE00000

    so, the exception class is 0b111111

    which…

    • Answered
    • 4 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • performance of floating point

    jinhong
    jinhong

    hi.

    I have a question about floating point performance relative with fpsr register.

    When i initialize hardware, there is floating point exception(inexactly floating-point exception).

    I did not set fpcr.IXE=0, so fpsr.IXC is set. not occur exception.

    …
    • 5 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Building Bazel and TensorFlow 2.x on AArch64

    Matthew Du Puy
    Matthew Du Puy

    Until recently, building TensorFlow at all on AArch64 was not possible due to its dependency on Bazel. Doing a bootstrap build of Bazel with its architecture-independent distribution archive failed. GitHub contributor, powderluv, has released several Bazel…

    • 5 months ago
    • Processors
    • Machine Learning IP blog
  • AArch64 Docker images for PyTorch and TensorFlow

    Jason Andrews
    Jason Andrews

    Docker images for TensorFlow and PyTorch running on Ubuntu 18.04 for Arm are now available. This article explains the details to build and use the Docker images for TensorFlow and PyTorch on Arm.

    TensorFlow and PyTorch are two of the most popular machine…

    • 5 months ago
    • Software Tools
    • Tools, Software and IDEs blog
  • ARM Base FVP freezes if left idle

    Mohannad Ismail
    Mohannad Ismail

    Greetings,

    If I leave the FVP idle for around 1 hour and come back to it, I find that it freezes and have to stop the simulation and re-run it again. What is the possible reason for this and is there a way to stop that from happening? Thank you for your…

    • 5 months ago
    • Tools and Software
    • Simulation Models forum
  • Some questions regarding ARMv8 hardware features

    Mohannad Ismail
    Mohannad Ismail

    Hello, 

    I am a PhD student doing research using the ARMv8 hardware features. I have a few questions regarding them. Some of these may seem a bit trivial, but I like to be a bit more thorough and confirm my understanding, and ARM is relatively new to me…

    • 6 months ago
    • Open Source Software and Platforms
    • Arm Development Platforms forum
  • compiler optimization options for ARMv8 GCC compiler on ARM cortex a53 (bare metal application)

    khan777
    khan777

    I am using ARMv8 GCC compiler(aarch64-none-elf-gcc) for my bare metal application on ARM cortex a53. I am using neon intrinsics with plain C in my code so I would like to ensure to use all optimization option available for this compiler.

    I tried -mfpu…

    • 7 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Optimization of Neon Intrinsics on ARM cortexa53

    khan777
    khan777

    I am using ARMv8 GCC compiler and I would like to optimize Neon Intrinsics code for better execution time performance. I have already tried loop unrolling and I am using look up table for the computation of log10. Any ideas?

    Here is the code:

    static inline…

    • 7 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Is there documentation somewhere to help folks develop their own UEFI/EBBR/SBBR to get rid of U-Boot?

    poddingue
    poddingue

    Hi there,

    I have not yet understood what "Arm Server Ready" means and what are its main advantages, but it looks like it is tightly linked to UEFI/SBBR.
    I have seen that some people were trying to create UEFI for the Raspberry Pi, so there must…

    • Answered
    • 8 months ago
    • Developer Community
    • Infrastructure Solutions
  • Debugging using DS5 and Foundation model: Interrupt is not forwarded to the CPU.

    Jorge
    Jorge

    Hi guys,

    I've been trying to implement and test a GICv2 driver on a Foundation model present in the tool ARM DS-5 and facing some issues with interrupts.

    I've enabled and set pending an interrupt in the GIC distributer and I actually see that is the…

    • 8 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Does MSR DAIF require ISB instruction? If no, why?

    scopichmu
    scopichmu

    Dear experts,

    I see a lot of code in opensource like

    .macro disable_daif
         msr     daifset, #0xf
    .endm
    


    and it doesn't apply ISB instruction after it. Though I read in ARM manual that:
    "context-changing operations
    that require the insertion…
    • Answered
    • 9 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • EDSCR err bit set after a write to EDITR

    kka
    kka

    Hi,

    I have a very similar question to the resolved entry "reason for ARMv8 EDSCR err bit set".

    So I try to follow that to give the state information.

    Cortex-57

    JTAG TCK = 3,788MHz.

    ARM_STATE_AARCH64 is set

    Before Halt state:

    EDPRSR = 0x1

    EDSCR…

    • 9 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • md_apply_fix when using trick to simulate __attribute__(at())

    Alex Earl
    Alex Earl

    I am using a "trick" to simulate __attribute__(at()) from the ARM toolchain in GCC. I have a macro defined as 

    #define __AT(name, addr) asm(".equ " #name ", " #addr)

    Then I have something like the following:

    extern volatile…

    • 9 months ago
    • Open Source Software and Platforms
    • GNU Toolchain forum
  • How to do from Secure(EL3) to Non-secure Exception level transition in ARMV8-A ?

    Mr_Sanjay
    Mr_Sanjay

    Hi all i trying do transition from EL3 to EL2 exception ,but after ERET of EL3 mode it change the mode to EL2 , but as soon as when it will execute first instruction of EL2 , then It goes to Exception ...

    This is happen for every secure to non secure transition…

    • 10 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM A64 Page table

    venmer
    venmer

    Hi,

    I have a question on ARM page table.

    I am running a bare metal application on Cortex A72 and i have a failure with my application.

    Upon debugging the failure, i found an address which is contributing the failure. our Bare metal application is responsible…

    • 11 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Is there any simple math library that is optimized for aarch64, like NE10 for v7

    Yusuke
    Yusuke

    I'm looking for a simple math library that is optimized for aarch64.

    NE10 looked perfect but I ended up finding that it doesn't support math functions for aarch64.

    Arm Compute Library looks a bit too much in my situation since I only need some…

    • 11 months ago
    • Open Source Software and Platforms
    • Machine Learning forum
  • Does the ThunderX CP processor support AArch32?

    cbowen
    cbowen

    It's my understanding that AArch64 is supposed to be backward compatible with AArch32, at least that is what the documentation says. But, I found one (1) page at https://en.wikichip.org/wiki/cavium/thunderx that says the ThunderX processors do not support…

    • 11 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Partial register dependency neon

    doofenstein
    doofenstein

    I'm having trouble finding any informations on partial neon register dependencies.

    Take for example the following code:

    ld2 {v0.16b, v1.16b}[0], [x0]
    ld2 {v0.16b, v1.16b}[1], [x1]
    ld2 {v0.16b, v1.16b}[2], [x2]
    ...

    Does the second load have to wait…

    • 11 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Atomic write (LDAXR/STLXR) causes infinite loop on Cortex-A72

    zhak
    zhak
    I have code which runs on Cortex-A72 (AArch64) and it disassembles to the following:
     0:   d53800a9    mrs x9, mpidr_el1
     4:   92400529    and x9, x9, #0x3
     8:   b4000069    cbz x9, 0x14
     c:   d503205f    wfe
    10:   17ffffff    b   0xc
    14:   10ffff69…
    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
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