Just in case someone needs them, I made ARM and Thumb mode lists of Cortex-A7 instructions (because I didn't find them in the net).

They are generated from ARMv7-A/R ARM with a simple AWK-script and then edited, so they may contain errors.

The lists…

Does anyone know if there is a list of ARM instruction set pseudo instructions?

Or better yet, an instruction list like PPC's, where there is a list of 'true instructions' with mnemonics and

another list of "simplified mnemonics" (=pseudo instructions…

Now that the funny PABT-behaviour is found to be (probably) caused ny debug state, I'd like to exit debug state before return from PABT exception. The ARM v7-A/R ARM says that I should write RRQ to DBGDRCR, but it seems that in Cortex-A7 it's not accessible…

I came across a weird behaviour when trying out my program on Raspberry Pi 2b (Cortex-A7):

When I try my PABT-handler using BKPT, the handler is entered fine, but on return the program restarts.

The restarted program returns fine from the BKPT and continues…

In my little program (rpi_stub) it's time to turn on MMU and caches.

Most of it I seem to have hold of, except cache invalidations.

In multicore situation (rpi_doesn't support yet, but maybe later), what needs to be invalidated and how?

I understand…

I was trying to write a register context saving/restoring when I came across a weird behaviour.

My code (sorry, tried to format tens of times, but the editor WANTS to make asm a table):

I've been trying to get a watchpoint to trigger, but no luck.

There should be 4 watchpoints accordíng to DBGDIDR, DBGDSCR=0x0204000e, so there shouldn't be any problems there?

I use (just in case) the cp14 interface - write DBGWVR0 and DBGWCR0…

In a Cortex-A7 is there a register that shows which breakpoint or watchpoint has triggered a debug event?

Or what's the usual way to find out?

I understand that DFSR FS tells if the DABT took place due to debug event (IFSR for PABT) and MOE in DBGDSCR…

It seems Arm9 requries, but A7 doesn't.

Hi,

Following are the query regarding the ARM Cortex A7 MP Core.

In ARM Cortex A7 MP Core,facing a issue in memory mapping the registers and accessing the registers by read and write operations.

By means of the reference manual the base configuration address…