Hi,
In AXI4/5 spec (IHI0022F), it listed a set of signal dependencies for read and write transactions.
My problem is in Figure A3-7 AXI4 and AXI5 write transaction handshake dependencies. It noted that "Dependencies on the assertion of WVALID also require…
Hi,
In AXI4, spec changed the definition of the definition of AxCACHE[3:2] from Write Allocate/Read Allocate to be Allocate/Other Allocate.
But is there any concrete reason for this change? Actually I found some related statements from spec, but I couldn…
Hi ,
What is the purpose of removing ID's (WID) in AXI4 ?
If it because of reduction of pin count then We lost the " Write Data Interleaving" and "Out Of Order " Transaction features. Can you please tell me if any other reasons...(Arm Spec says.…
Hi Folks,
We need a clarification on Read Data Interleaving on AXI4
Read Data Interleaving is supported in AXI4 and following is my understanding on Data Interleaving:
Multiple Read commands can be executed simultaneously and data interleaving is supported…
Could you please help me on this topics in AXI4 protocal ::
1. what is meant by Aligned and Unaligned address?
2.How can I calculate WRAP boundary calculation in AXI4? please explain with example?
Hi All ,
Can anyone please tell the difference btw AXI3 and AXI4.
Regards
Muthuvenkatesh
hi,
what are the purpose of interconnect..?and why we nedd address routing table..in axi4
I am new to AXI4 protocol. I would like to know how many clock cycles are required to complete a AXI4 burst write transaction.
Eg. Burst length- Two , Burst size 16 bytes.
Please give me answers for different types of data bus width say for bus width …
