• response ordering at AXI4 slave

    rvora
    rvora

    1) is response ordering logic need to be developed at Slave side?

    2) Consider Single master-Single slave connection, master issue the outstanding read command to slave with following transaction

               1st transaction:   ARID =4, ARLEN=10

               2nd transaction…

    • Answered
    • 2 months ago
    • System
    • SoC Design forum
  • Can AHB3_Lite master send an unaligend address?

    Jerry_cn
    Jerry_cn

    AHB3_Lite protocol has a paragraph that "All transfers in a burst must be aligned to the address boundary equal to the size of the transfer. For example, you must align word transfers to word address boundaries
    (HADDR[1:0] = b00), and halfword transfers…

    • Answered
    • 3 months ago
    • System
    • SoC Design forum
  • Is AXI4 Ordered write observation used to support PCIE Producer/Consumer ordering model?

    zhibo05
    zhibo05

    AXI4 spec "Ordered write observation" says it "can support the Producer/Consumer ordering model with improved performance". AXI4 spec does not mention PCIE spec, but we know PCIE spec uses Producer/Consumer ordering model.

    For instance…

    • Answered
    • 5 months ago
    • System
    • SoC Design forum
  • AXI4 Bus Bandwidth/Data Transfer increase

    willo144
    willo144

    Hello,

    I am doing research with an Ultra-Embedded Implementation of a RISC-V Processor in gem5.  My team is using an Oracle Virtual Machine to run testbenches and benchmarks for our research motivation.  As part of our research, I have been tasked with…

    • 7 months ago
    • System
    • SoC Design forum
  • ARM AMBA AXI4 read channel information

    Ravi V.
    Ravi V.

    Hello,

    If AXI4 master issue read transfer by asserting the ARADDR = 0x0002, of ARSIZE = 0, ARLEN = 0, on which byte lane of RDATA slave drive the read data byte?

    Guide me with sort and simple answer!

    Thank you!

    • Answered
    • 8 months ago
    • System
    • SoC Design forum
  • Help with AXI4 payload with data bus width of 32 bits

    KarthikRao
    KarthikRao

    Hello All, I am referring to the ARM AMBA TLM 2.0 guide. I am trying to send around 50KB of data through AXI4 protocol. Here it uses the AXI4 payload and not the generic payload. My data bus width is 32 bits. 1 data beat would mean 4 bytes so I can send…

    • 8 months ago
    • System
    • SoC Design forum
  • Readunique and cleanunique transactions in ACE protocol

    het
    het

    In case of readunique transaction cache line is copied into the initiating master's cache(whether it is clean or dirty) and invalidated in snooped master's cache and then store operaation is performed in initiating master's cache line.

    In…

    • 10 months ago
    • System
    • Embedded forum
  • Inconsistency in latest AXI4 specification (version g) regarding INCR burst transfers.

    MuchToLearn
    MuchToLearn
    There seems to be a slight inconsistency in the following paragraph about INCR burst transfers on page A3-50:
     
    In an incrementing burst, the address for each transfer in the burst is an increment of the address for the previous transfer. The increment…
    • 11 months ago
    • System
    • SoC Design forum
  • I am working on AXI vip and I am confused about where should I put logic about burst(FIXED,INCR,WRAP) can anybody give me direction ?

    pure
    pure

    at which side I can declare logic about burst kind .at master side or slave side.

    • 11 months ago
    • System
    • SoC Design forum
  • AXI fixed burst to a slave with narrow data width

    Sana
    Sana

    Hi,

    I have an AXI master with data width 64, and an AHB slave of data width 32. What would happen when there is a 64bit FIXED burst READ (i.e., asize=3)to an address 0X100 of the slave? 

    Would the the data be read from 0x100 only, with data[63:32] always…

    • over 1 year ago
    • System
    • SoC Design forum
  • Aligned and unaligned word transfers on a 64-bit bus

    Maria_d
    Maria_d

    address = 0x07 

    transfer size = 32 bit

    burst type  = INC

    Burst length = 4 transfers

    Can you please explain this example of unaligned word transfer on 64-bit bus.

    Why the second transfer started at 8 and not from C?

    • over 1 year ago
    • System
    • SoC Design forum
  • Is there a limit for AXI4 outstanding transaction?

    ShimmyLee
    ShimmyLee

    Hi all!  I'm working on an avalon to axi4 master writing  bridge module. In many cases,I need to assert a large number of awvalid continually for writing efficiency(for instance, a frame of  4K video data) 

    How many awvalid can i assert continually in…

    • over 1 year ago
    • System
    • SoC Design forum
  • what action will be performed by the master based on the read and write responce in axi 4?

    Hem Patel
    Hem Patel

    i read the specification of AXI 4 protocol. i want to know what action will be performed by the master when it receive okay,exokay,slverr or decerr. okay and exokay says that the transfer is completed either by normal access and by the exclusive access…

    • Answered
    • over 1 year ago
    • System
    • SoC Design forum
  • Axi4 Write Transaction

    SelvamThangam
    SelvamThangam

    I got a doubt,Does Master should wait for Bresp to send next Write transaction or it can continuously send the transaction independent for Bresp.

    • over 1 year ago
    • System
    • SoC Design forum
  • AXI-4 questions

    SBR_123
    SBR_123

    Hello,

    I am pretty new to AMBA protocol and I am specifically interested in AXI-4. I have a few fundamental questions related to AXI-4 and I would appreciate if anyone can answer these.

    1) I would like to know how read and write address requests issued…

    • Answered
    • over 4 years ago
    • System
    • Embedded forum
  • Removal of WID's in AMBA AXI4

    mvenkatesh
    mvenkatesh

    Hi ,

       What is the purpose of removing ID's (WID) in AXI4 ?

    If it because of reduction of pin count then We lost the " Write Data Interleaving" and "Out Of Order " Transaction features. Can you please tell me if any other reasons...(Arm Spec says.…

    • over 1 year ago
    • System
    • Embedded forum
  • ARM AXI4 protocol assertions trigger errm_wdata_num_prop5 and errm_wlast_stable quesitons

    armchronos
    armchronos

    Hi,

    I'm getting two AXI4 protocol assertion errors.

    For axi4_errm_wlast_stable, I can see why it's flagging an error but functionally it shouldn't be a problem.

    The WREADY =1 for one more cycle when though WVALID=0 and WLAST=0. 

    Is this a…

    • Answered
    • over 3 years ago
    • System
    • SoC Design forum
  • Is during AXI unaligned transfer not all WDATA bits used?

    hayk
    hayk

    Dear Forum,

    Can you please confirm one thing.

    When we have un-aligned transfer, do some of WDATA bits not used during that transfer?

    For example, in the below unaligned transfer WDATA[7:0] are not used for the 1st transfer. Is my understanding right?

    …
    • over 1 year ago
    • System
    • SoC Design forum
  • When Wrapping happens in AXI?

    hayk
    hayk

    Hi Forum,

    I cannot understand when address is being wrapped in WRAP burst.In my example, the WRAP condition never happens in other words, during BURST operation address always remains small than wrap address.

    From the spec, the wrapping happens when

    …
    • over 1 year ago
    • System
    • SoC Design forum
  • Regarding WRAP burst calculation in AXI4

    pavan316
    pavan316

    Could you please help me on this topics in AXI4 protocal ::

    1. what is meant by Aligned and Unaligned address?

    2.How can I calculate WRAP boundary calculation in AXI4? please explain with example?

    • Answered
    • over 2 years ago
    • System
    • SoC Design forum
  • needs some clarification

    bala devi
    bala devi

    Difference between axi_4 and axi4_alite?

    • Answered
    • over 2 years ago
    • System
    • SoC Design forum
  • Difference btw AXI3 and AXI4

    Muthuvenkatesh
    Muthuvenkatesh

    Hi All ,

                Can anyone please tell the difference btw AXI3 and AXI4.

    Regards

    Muthuvenkatesh

    • Answered
    • over 2 years ago
    • System
    • SoC Design forum
  • needs some clarifiaction

    bala devi
    bala devi

    hi,

    what are the purpose of interconnect..?and why we nedd address routing table..in axi4

    • over 2 years ago
    • System
    • SoC Design forum
  • AXI4 Burst Transactions

    surajrgupta
    surajrgupta

    I am new to AXI4 protocol. I would like to know how many clock cycles are required to complete a AXI4 burst write transaction.

    Eg. Burst length- Two , Burst size 16 bytes.

    Please give me answers for different types of data bus width say for bus width …

    • Answered
    • over 1 year ago
    • System
    • SoC Design forum
  • Why AXI4 changed the definition of AxCACHE?

    Yu-Hsin
    Yu-Hsin

    Hi,

    In AXI4, spec changed the definition of the definition of AxCACHE[3:2] from Write Allocate/Read Allocate to be Allocate/Other Allocate.

    But is there any concrete reason for this change? Actually I found some related statements from spec, but I couldn…

    • over 1 year ago
    • System
    • Embedded forum
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