In AXI4 Stream protocol apart from data byte two other byte types are defined known as position byte and null byte. 

For the position byte the description says: "A byte that indicates the relative positions of data bytes within the stream. This is a placeholder…

Hello I am  new to AXI and just saw the pseudocode for a transfer in the spec of AXI . My question is regarding Data_Bus_Bytes .

Q1-  The spec says that Data_Bus_Bytes is  number of 8 bit byte lanes in the bus. Is it same  as Number_Bytes which is 2^AWSIZE…

Can somebody please explain how barrier transactions in ACE work?

Thanks in advance.

A master wants to initiate write transfers to two different slaves whose address ranges are consequtive   can he choose to initiate write transfer starting in 1st slave address range and choose ASIZE and ALEN such that second slave is also covered? if yes…

Hello,

I am unable to understand , which start address should i take in case of wrapping burst address calculation of AXI?

For example , 

my Burst size=4 transfers(beats)

each beat(transfer)size=4bytes=32bits.

hence total size of burst=32*8=256bits. Hence…

Hi,

We are using Cortex-R5F. Through the AXI slave interface, we are accessing the data cache data RAM, tag RAM and dirty RAM. We would like to know how we can associate the bits found in the data RAM with the bits found in the tag RAM. For example,…

Hi,

In the AXI spec it is mentioned that , even in case of ERROR response, the slave needs to respond with the exact number of beats and indicate the response with each beat.

Now my question here is if the response is going to be ERROR(lets say SLVERR…

Hi,

In AXI4, spec changed the definition of the definition of AxCACHE[3:2] from Write Allocate/Read Allocate to be Allocate/Other Allocate.

But is there any concrete reason for this change? Actually I found some related statements from spec, but I couldn…

In Section C1.3 Channel Overview of the AMBA_AXI_and_ACE protocol specifications, It is mentioned under "Store operations where the cache line is already cached" as :

The initiating master component requests a unique copy of the cache line…

Hi ,

   What is the purpose of removing ID's (WID) in AXI4 ?

If it because of reduction of pin count then We lost the " Write Data Interleaving" and "Out Of Order " Transaction features. Can you please tell me if any other reasons...(Arm Spec says.…

Hi,

I have a question about the correct behavior when performing a narrow read with an unaligned address; consider the following scenario:

- 32 bit data bus

- address x0001

- length 0 (1 beat)

- size 1 (2 byte)

My interpretation of the spec is that in…

I am implementing Read Modified Write on SRAM through AXI. What is the role of awsize and wstrbe?

Say data width is 64 bits, and awsize is set to support 64-bits, but the underlying wstrbe are only valid for lower 32-bits (8'b0000_1111). Does this candid…

In AXI Write how the handshake between AW channel and B channel is taken care.

Standard says that 

"the slave must wait for both WVALID and WREADY to be asserted before asserting BVALID"

Does that means BVALID will never be asserted in the same…

I have one question for QoS with AXI4:

Can one master have multiple QoS values?

Meaning one master issues requests with different QoS values but all with same AXI ID and the interconnect network arbitrates between these requests based on QoS value and…

Hi,

I'm getting two AXI4 protocol assertion errors.

For axi4_errm_wlast_stable, I can see why it's flagging an error but functionally it shouldn't be a problem.

The WREADY =1 for one more cycle when though WVALID=0 and WLAST=0. 

Is this a…

The AXI protocol description states for modifiable transactions (ARCACHE[1] is asserted):

"a read transaction can fetch more data than required"

To me, this can be interpreted in two ways:

1. The RVALID signal of the slave can be asserted for…

Hi,

I am working on AXI bus for my college project. For my work I have to add something new in existing architecture. Can someone provide me idea for my work? 

Hi ARM/arktos,

Seems like this online discussion is not working properly.

I ask a question, you reply, and if I reply the discussion tool doesn't echo back my reply by email.

So most likely you may not see it.

Below is my reply to your answer to my…

In the spec it is mentioned that AXI4 supports high-bandwidth, high-frequency and low-latency operation. How to justify this?  What is the meaning of bandwidth in this context? What are the  values of bandwidth and frequency? How they decide the operating…

I want to know what happens in these scenarios :
1) Assume Master1 (M1) is doing locked access, if locked access fails before M1 does unlocking transaction what is the response to the M1?
2) Assume M1 is doing locked transaction, if other Master2 (M2)…

Hi,

I assume CHI needs to either pipeline or implement something like the AXI register slice to support long distance connections.

Please confirm and where can I find relevant information for this topic.

Thanks,

David

Hi,

 I have tried to find a quick reference for AXI, AHB & APB to no avail, and after having to flit between the various documents and tables, I eventually created my own.

So not sure of the legal ramifications of posting this elsewhere and whether…