Hi,

We are using Cortex-R5F. Through the AXI slave interface, we are accessing the data cache data RAM, tag RAM and dirty RAM. We would like to know how we can associate the bits found in the data RAM with the bits found in the tag RAM. For example,…

Hi,

In AXI4/5 spec (IHI0022F), it listed a set of signal dependencies for read and write transactions.

My problem is in Figure A3-7 AXI4 and AXI5 write transaction handshake dependencies. It noted that "Dependencies on the assertion of WVALID also require…

Hi,

In the AXI spec it is mentioned that , even in case of ERROR response, the slave needs to respond with the exact number of beats and indicate the response with each beat.

Now my question here is if the response is going to be ERROR(lets say SLVERR…

Hi,

In AXI4, spec changed the definition of the definition of AxCACHE[3:2] from Write Allocate/Read Allocate to be Allocate/Other Allocate.

But is there any concrete reason for this change? Actually I found some related statements from spec, but I couldn…

In Section C1.3 Channel Overview of the AMBA_AXI_and_ACE protocol specifications, It is mentioned under "Store operations where the cache line is already cached" as :

The initiating master component requests a unique copy of the cache line…

Hi ,

   What is the purpose of removing ID's (WID) in AXI4 ?

If it because of reduction of pin count then We lost the " Write Data Interleaving" and "Out Of Order " Transaction features. Can you please tell me if any other reasons...(Arm Spec says.…

What is byte lane in AXI?

In read transfres how the slave indicates the transaction is over?

If the slave is not able to process read request from master, which response is expected from slave?

Why burst must not cross 4kb  in AXI ?

Hii,

Greetings !!

I would like to know the standard operating clock frequency and data rate of AMBA- apb, ahb, axi.

Please someone help me out.

Thanks in advance

Regards

Ujjwal

what is the difference between overlapping and out of order transfers in Aciform the explanation it seems that both are same is this the case?

Why the word boundary in AXI is 4k?

Consider Data interface is 64 bit.
It is Write transfer.
AXI master need to transfer 11 bytes and starting address is 0. Anyone suggest which one is a valid among below mentioned two scenarios.

Scenario 1:
Burst -> Address:0, size:3, length:1, burst_type…

Use case which come to my mind is.

1. Display controller might need to flip an image 180 degrees. Here memory reading pattern is reversed.

2. Where ever there is LIFO (Last In Fist Out) implementations.

Hi All,

                       I am doing single write operation to AXI slave from avalon BFM. The data and address signals

are reached into the axi slave.But if i am try to read back the data which i have written in the same location,the data is  not matched.

It…

Is interleave and reorder the same concept?

My interpretation is a slave can reorder without interleaving, which means entire read burst are reordered with no interleaving. So my understanding is they are different. Confirm my understanding.

why we need write strobe signal in axi where we generate in our verif env

Thanks

what happen if WVALID asserted before AWVALID ??

Hi,

I am creating a systemC model for a peripheral which has an AXI4 interface.

Is there a bit and pin accurate AXI4 SystemC model similar to the ones available for OCP?

Is it available from ARM, a ThirdParty vendor, or the opensource community?

I am new to AXI4 protocol. I would like to know how many clock cycles are required to complete a AXI4 burst write transaction.

Eg. Burst length- Two , Burst size 16 bytes.

Please give me answers for different types of data bus width say for bus width …