ARM Cortex ICode, DCode, System buses

Felix Varghese

Note: This was originally posted on 26th February 2009 at http://forums.arm.com

I'm a bit confused about the bus structure and memory model of ARM Cortex M3. First of all, does Cortex M3 actually have 3 physically separate buses coming out of it?

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over 6 years ago
System
SoC Design forum

SRAM for Cortex M0 -- Does It Need to Support Byte write?

Ming

For the SRAM with Cortex M0, does it need to support byte write?

What restrictions do I have with Cortex M0 if the SRAM only support 32-bit write?

over 5 years ago
System
SoC Design forum

RMW operation on SRAM via AXI

niket

I am implementing Read Modified Write on SRAM through AXI. What is the role of awsize and wstrbe?

Say data width is 64 bits, and awsize is set to support 64-bits, but the underlying wstrbe are only valid for lower 32-bits (8'b0000_1111). Does this candid…

Answered

over 3 years ago
System
SoC Design forum

About two port SRAM compiler in tsmc 0.13um ?

Fuyongwen

Hi,

I only found signle and dual-port sram compiler in tsmc 0.13µm process IP Library,.

Doesn't ARM support the two port SRAM compiler for tsmc 0.13µm process?

Thank you

Answered

over 6 years ago
System
SoC Design forum