Hi,

I was reading the CHI architecture specification but there is no mention of electrical characteristics such as

the clock frequency for the CHI interface.

What is the max and min frequency for CHI interface ?

Thanks,

David

What is byte lane in AXI?

In read transfres how the slave indicates the transaction is over?

If the slave is not able to process read request from master, which response is expected from slave?

Why burst must not cross 4kb  in AXI ?

Hii,

Greetings !!

I would like to know the standard operating clock frequency and data rate of AMBA- apb, ahb, axi.

Please someone help me out.

Thanks in advance

Regards

Ujjwal

what is the difference between overlapping and out of order transfers in Aciform the explanation it seems that both are same is this the case?

Why the word boundary in AXI is 4k?

Consider Data interface is 64 bit.
It is Write transfer.
AXI master need to transfer 11 bytes and starting address is 0. Anyone suggest which one is a valid among below mentioned two scenarios.

Scenario 1:
Burst -> Address:0, size:3, length:1, burst_type…

  1.In AHB except a single transfer inset a wait state in middle of the burst only or insert anywhere in a burst.

  2. In INCR burst transfer can i insert a BUSY in a middle of the burst or must insert a last of the burst.

Use case which come to my mind is.

1. Display controller might need to flip an image 180 degrees. Here memory reading pattern is reversed.

2. Where ever there is LIFO (Last In Fist Out) implementations.

Hi All,

                       I am doing single write operation to AXI slave from avalon BFM. The data and address signals

are reached into the axi slave.But if i am try to read back the data which i have written in the same location,the data is  not matched.

It…

Is interleave and reorder the same concept?

My interpretation is a slave can reorder without interleaving, which means entire read burst are reordered with no interleaving. So my understanding is they are different. Confirm my understanding.

why we need write strobe signal in axi where we generate in our verif env

Thanks

Hi,

Can any one explain me how address decoding is done in amba ahb?

HRESP  is given  for address or data??

hi,

Is HREADY is used by the slave  to notify the master that it is ready to receive or to indicate transfer is completed??

thanks in advance

Could you please help me on this topics in AXI4 protocal ::

1. what is meant by Aligned and Unaligned address?

2.How can I calculate WRAP boundary calculation in AXI4? please explain with example?

what happen if WVALID asserted before AWVALID ??

In case of AXI4 lite protocol,whether BValid should be asserted before WVALID signal deassertion? what is the legal case?

In specification it is mentioned that WREADY signal can wait for AWVALID and WVALID signals.

Does it mean that WREADY signal should be asserted only after assertion of AWVALID and WVALID signals.

What is the relation between these signals?

and performance…

Hi All,

                           I have doubt in ahb_lite hresp signaling when the address phase is extending.

In the following diagram transfer address c is extending because of data phase of B.

In 3rd clk cycle address C is sampled so that shall we expect the…