I am a experinced VLSI/ASIC logic design engineer living in Israel who wants to educate himself FPGA design with embedded ARM on the private basis. Please, advise on the better path how to do that. For example, "go to this ARM site link such and such…
Bypassing all clock gates in Cortex-R52 (ARMv8)
Hello,
(#context): I have a Cortex-R52 in the SoC design. My team is in charge of FPGA prototyping of the entire/part of the SoC. I am prototyping (on FPGA) part of the SoC which has the R52 plus some other IPs.
(#problem): It's not possible to close…
- over 1 year ago
- System
- SoC Design forum
Partial Word Access to Altera Avalon Memory-Mapped Slave
when I say partial word access, I mean 16-bit (two byte) or 8-bit (byte) read/write.
Background:
In one of our recent projects, Cyclone V SoC is used to replace 386 CPU in an existing product.
I am responsible for the board and FPGA design. Another software…
- over 4 years ago
- System
- SoC Design forum
Can the ARM corrupt the timing on the AXI bus
I have a Cyclone V SOC system, and the ARM is running Linux, and the FPGA is running SDI video and VIP suite items. The FPGA DDR memory is being used by the VIP suite and all works well. The ARM is using the DDR memory attached to it, and Linux does not…
- over 1 year ago
- System
- SoC Design forum