• Handling invalid AXI address requests

    EBB
    EBB

    I'm working with the Cortex-M on digilent ARTY FPGA platform. I'm wondering how handling invalid address requests happen on a typical system. I'm guessing the address decoder in the AXI crossbar interconnect handles it somehow. Does it return an error…

    • Answered
    • 7 months ago
    • System
    • SoC Design forum
  • Bus Matrix

    Felix Varghese
    Felix Varghese
    Note: This was originally posted on 28th January 2009 at http://forums.arm.com

    What exactly is a bus matrix? I came across the term in ARM cortex M3 specs but couldnt find any proper description. Can someone help?
    • over 6 years ago
    • System
    • SoC Design forum
  • ARM Cortex ICode, DCode, System buses

    Felix Varghese
    Felix Varghese
    Note: This was originally posted on 26th February 2009 at http://forums.arm.com

    I'm a bit confused about the bus structure and memory model of ARM Cortex M3. First of all, does Cortex M3 actually have 3 physically separate buses coming out of it?
    …
    • over 6 years ago
    • System
    • SoC Design forum
  • Flashing STM32L0

    sarthak.kelapure
    sarthak.kelapure

    I have made a custom board for STM32L072CZ by ST. I am flashing it using STM32Cube Programmer via UART. When I flash it, I get the application running(say blinking LED) for the first time and as soon as I reset it, the application stops running. I checked…

    • over 2 years ago
    • System
    • SoC Design forum
  • SRAM for Cortex M0 -- Does It Need to Support Byte write?

    Ming
    Ming

    For the SRAM with Cortex M0, does it need to support byte write?

    What restrictions do I have with Cortex M0 if the SRAM only support 32-bit write?

    • over 5 years ago
    • System
    • SoC Design forum
  • Is the Corelink SSE-200 Subsystem available for Cortex M23?

    Mike EFTIMAKIS
    Mike EFTIMAKIS

    This question was raised in the 'How to implement a secure IoT system on ARMv8-M' webinar, view all the questions in the round up blog post. 

     
    • Answered
    • over 3 years ago
    • System
    • SoC Design forum
  • Can you explain why you propose having two cores in your CoreLink SSE-200?

    Mike EFTIMAKIS
    Mike EFTIMAKIS

    This question was raised in the 'How to implement a secure IoT system on ARMv8-M' webinar, view all the questions in the round up blog post. 

    • Answered
    • over 3 years ago
    • System
    • SoC Design forum
  • Does Cortex-M33 support TCMs?

    Ed Player
    Ed Player

    This question was raised in the 'How to implement a secure IoT system on ARMv8-M' webinar, view all the questions in the round up blog post. 

    • Answered
    • over 3 years ago
    • System
    • SoC Design forum
  • Could you give some tips on developing for ARMv8-M with IAR tools?

    Ed Player
    Ed Player

    This question was raised in the 'How to implement a secure IoT system on ARMv8-M' webinar, view all the questions in the round up blog post. 

    • Answered
    • over 3 years ago
    • System
    • SoC Design forum
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